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| Rev | Author | Line No. | Line |
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| 1 | jermar | 1 | /* |
| 3982 | jermar | 2 | * Copyright (c) 2009 Jakub Jermar |
| 1 | jermar | 3 | * All rights reserved. |
| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 1754 | jermar | 29 | /** @addtogroup genarch |
| 1702 | cejka | 30 | * @{ |
| 31 | */ |
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| 1754 | jermar | 32 | /** |
| 1757 | jermar | 33 | * @file |
| 4042 | jermar | 34 | * @brief Zilog 8530 serial controller driver. |
| 1702 | cejka | 35 | */ |
| 36 | |||
| 4042 | jermar | 37 | #include <genarch/drivers/z8530/z8530.h> |
| 511 | jermar | 38 | #include <console/chardev.h> |
| 3961 | jermar | 39 | #include <ddi/irq.h> |
| 40 | #include <arch/asm.h> |
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| 41 | #include <mm/slab.h> |
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| 1 | jermar | 42 | |
| 3961 | jermar | 43 | static inline void z8530_write(ioport8_t *ctl, uint8_t reg, uint8_t val) |
| 44 | { |
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| 45 | /* |
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| 46 | * Registers 8-15 will automatically issue the Point High |
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| 47 | * command as their bit 3 is 1. |
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| 48 | */ |
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| 49 | pio_write_8(ctl, reg); /* select register */ |
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| 50 | pio_write_8(ctl, val); /* write value */ |
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| 51 | } |
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| 52 | |||
| 53 | static inline uint8_t z8530_read(ioport8_t *ctl, uint8_t reg) |
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| 54 | { |
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| 55 | /* |
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| 56 | * Registers 8-15 will automatically issue the Point High |
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| 57 | * command as their bit 3 is 1. |
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| 58 | */ |
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| 59 | pio_write_8(ctl, reg); /* select register */ |
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| 60 | return pio_read_8(ctl); |
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| 61 | } |
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| 62 | |||
| 63 | /** Initialize z8530. */ |
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| 64 | bool |
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| 4042 | jermar | 65 | z8530_init(z8530_t *dev, devno_t devno, inr_t inr, cir_t cir, void *cir_arg, |
| 66 | chardev_t *devout) |
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| 1 | jermar | 67 | { |
| 3961 | jermar | 68 | z8530_instance_t *instance; |
| 1944 | jermar | 69 | |
| 3961 | jermar | 70 | instance = malloc(sizeof(z8530_instance_t), FRAME_ATOMIC); |
| 71 | if (!instance) |
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| 72 | return false; |
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| 73 | |||
| 74 | instance->devno = devno; |
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| 75 | instance->z8530 = dev; |
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| 4042 | jermar | 76 | instance->devout = devout; |
| 3961 | jermar | 77 | |
| 78 | irq_initialize(&instance->irq); |
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| 79 | instance->irq.devno = devno; |
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| 80 | instance->irq.inr = inr; |
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| 81 | instance->irq.claim = z8530_claim; |
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| 82 | instance->irq.handler = z8530_irq_handler; |
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| 83 | instance->irq.instance = instance; |
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| 84 | instance->irq.cir = cir; |
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| 85 | instance->irq.cir_arg = cir_arg; |
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| 86 | irq_register(&instance->irq); |
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| 87 | |||
| 88 | (void) z8530_read(&dev->ctl_a, RR8); |
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| 89 | |||
| 1925 | jermar | 90 | /* |
| 91 | * Clear any pending TX interrupts or we never manage |
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| 92 | * to set FHC UART interrupt state to idle. |
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| 93 | */ |
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| 3961 | jermar | 94 | z8530_write(&dev->ctl_a, WR0, WR0_TX_IP_RST); |
| 1925 | jermar | 95 | |
| 3655 | jermar | 96 | /* interrupt on all characters */ |
| 3961 | jermar | 97 | z8530_write(&dev->ctl_a, WR1, WR1_IARCSC); |
| 1925 | jermar | 98 | |
| 99 | /* 8 bits per character and enable receiver */ |
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| 3961 | jermar | 100 | z8530_write(&dev->ctl_a, WR3, WR3_RX8BITSCH | WR3_RX_ENABLE); |
| 1925 | jermar | 101 | |
| 3655 | jermar | 102 | /* Master Interrupt Enable. */ |
| 3961 | jermar | 103 | z8530_write(&dev->ctl_a, WR9, WR9_MIE); |
| 1849 | jermar | 104 | |
| 3961 | jermar | 105 | return true; |
| 1 | jermar | 106 | } |
| 107 | |||
| 3961 | jermar | 108 | irq_ownership_t z8530_claim(irq_t *irq) |
| 878 | vana | 109 | { |
| 3961 | jermar | 110 | z8530_instance_t *instance = irq->instance; |
| 111 | z8530_t *dev = instance->z8530; |
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| 878 | vana | 112 | |
| 4042 | jermar | 113 | if (z8530_read(&dev->ctl_a, RR0) & RR0_RCA) |
| 114 | return IRQ_ACCEPT; |
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| 115 | else |
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| 116 | return IRQ_DECLINE; |
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| 878 | vana | 117 | } |
| 895 | jermar | 118 | |
| 3961 | jermar | 119 | void z8530_irq_handler(irq_t *irq) |
| 895 | jermar | 120 | { |
| 3961 | jermar | 121 | z8530_instance_t *instance = irq->instance; |
| 122 | z8530_t *dev = instance->z8530; |
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| 1780 | jermar | 123 | uint8_t x; |
| 895 | jermar | 124 | |
| 3961 | jermar | 125 | if (z8530_read(&dev->ctl_a, RR0) & RR0_RCA) { |
| 126 | x = z8530_read(&dev->ctl_a, RR8); |
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| 4042 | jermar | 127 | if (instance->devout) |
| 128 | chardev_push_character(instance->devout, x); |
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| 895 | jermar | 129 | } |
| 130 | } |
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| 1702 | cejka | 131 | |
| 1754 | jermar | 132 | /** @} |
| 1702 | cejka | 133 | */ |