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| Rev | Author | Line No. | Line |
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| 156 | decky | 1 | /* |
| 2071 | jermar | 2 | * Copyright (c) 2005 Martin Decky |
| 156 | decky | 3 | * All rights reserved. |
| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 1888 | jermar | 29 | /** @addtogroup ppc32 |
| 1702 | cejka | 30 | * @{ |
| 31 | */ |
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| 32 | /** @file |
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| 33 | */ |
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| 34 | |||
| 1888 | jermar | 35 | #ifndef KERN_ppc32_BARRIER_H_ |
| 36 | #define KERN_ppc32_BARRIER_H_ |
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| 156 | decky | 37 | |
| 1267 | decky | 38 | #define CS_ENTER_BARRIER() asm volatile ("" ::: "memory") |
| 39 | #define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") |
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| 156 | decky | 40 | |
| 1267 | decky | 41 | #define memory_barrier() asm volatile ("sync" ::: "memory") |
| 42 | #define read_barrier() asm volatile ("sync" ::: "memory") |
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| 43 | #define write_barrier() asm volatile ("eieio" ::: "memory") |
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| 177 | jermar | 44 | |
| 4055 | trochtova | 45 | /* |
| 46 | * The IMB sequence used here is valid for all possible cache models |
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| 47 | * on uniprocessor. SMP might require a different sequence. |
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| 48 | * See PowerPC Programming Environment for 32-Bit Microprocessors, |
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| 49 | * chapter 5.1.5.2 |
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| 50 | */ |
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| 51 | |||
| 52 | static inline void smc_coherence(void *addr) |
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| 53 | { |
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| 54 | asm volatile ( |
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| 55 | "dcbst 0, %0\n" |
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| 56 | "sync\n" |
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| 57 | "icbi 0, %0\n" |
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| 58 | "sync\n" |
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| 59 | "isync\n" |
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| 60 | :: "r" (addr) |
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| 61 | ); |
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| 62 | } |
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| 63 | |||
| 64 | #define COHERENCE_INVAL_MIN 4 |
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| 65 | |||
| 66 | static inline void smc_coherence_block(void *addr, unsigned long len) |
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| 67 | { |
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| 68 | unsigned long i; |
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| 69 | |||
| 70 | for (i = 0; i < len; i += COHERENCE_INVAL_MIN) { |
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| 71 | asm volatile ("dcbst 0, %0\n" :: "r" (addr + i)); |
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| 72 | } |
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| 73 | |||
| 74 | asm volatile ("sync"); |
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| 75 | |||
| 76 | for (i = 0; i < len; i += COHERENCE_INVAL_MIN) { |
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| 77 | asm volatile ("icbi 0, %0\n" :: "r" (addr + i)); |
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| 78 | } |
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| 79 | |||
| 80 | asm volatile ( |
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| 81 | "sync\n" |
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| 82 | "isync\n" |
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| 83 | ); |
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| 84 | } |
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| 85 | |||
| 156 | decky | 86 | #endif |
| 1702 | cejka | 87 | |
| 1888 | jermar | 88 | /** @} |
| 1702 | cejka | 89 | */ |