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2464 | jermar | 1 | /* |
2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
29 | /** @addtogroup arm32mm |
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30 | * @{ |
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31 | */ |
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32 | /** @file |
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33 | * @brief Page fault related functions. |
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34 | */ |
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35 | #include <panic.h> |
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36 | #include <arch/exception.h> |
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37 | #include <arch/mm/page_fault.h> |
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38 | #include <mm/as.h> |
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39 | #include <genarch/mm/page_pt.h> |
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40 | #include <arch.h> |
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41 | #include <interrupt.h> |
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4055 | trochtova | 42 | #include <print.h> |
2464 | jermar | 43 | |
44 | /** Returns value stored in fault status register. |
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45 | * |
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46 | * @return Value stored in CP15 fault status register (FSR). |
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47 | */ |
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48 | static inline fault_status_t read_fault_status_register(void) |
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49 | { |
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50 | fault_status_union_t fsu; |
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4055 | trochtova | 51 | |
2464 | jermar | 52 | /* fault status is stored in CP15 register 5 */ |
53 | asm volatile ( |
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4055 | trochtova | 54 | "mrc p15, 0, %[dummy], c5, c0, 0" |
55 | : [dummy] "=r" (fsu.dummy) |
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2464 | jermar | 56 | ); |
4055 | trochtova | 57 | |
2464 | jermar | 58 | return fsu.fs; |
59 | } |
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60 | |||
61 | /** Returns FAR (fault address register) content. |
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62 | * |
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63 | * @return FAR (fault address register) content (address that caused a page |
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4055 | trochtova | 64 | * fault) |
2464 | jermar | 65 | */ |
66 | static inline uintptr_t read_fault_address_register(void) |
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67 | { |
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68 | uintptr_t ret; |
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4055 | trochtova | 69 | |
2464 | jermar | 70 | /* fault adress is stored in CP15 register 6 */ |
71 | asm volatile ( |
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4055 | trochtova | 72 | "mrc p15, 0, %[ret], c6, c0, 0" |
73 | : [ret] "=r" (ret) |
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2464 | jermar | 74 | ); |
4055 | trochtova | 75 | |
2464 | jermar | 76 | return ret; |
77 | } |
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78 | |||
79 | /** Decides whether the instruction is load/store or not. |
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80 | * |
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81 | * @param instr Instruction |
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82 | * |
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83 | * @return true when instruction is load/store, false otherwise |
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4055 | trochtova | 84 | * |
2464 | jermar | 85 | */ |
86 | static inline bool is_load_store_instruction(instruction_t instr) |
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87 | { |
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88 | /* load store immediate offset */ |
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4055 | trochtova | 89 | if (instr.type == 0x2) |
2464 | jermar | 90 | return true; |
4055 | trochtova | 91 | |
2464 | jermar | 92 | /* load store register offset */ |
4055 | trochtova | 93 | if ((instr.type == 0x3) && (instr.bit4 == 0)) |
2464 | jermar | 94 | return true; |
4055 | trochtova | 95 | |
2464 | jermar | 96 | /* load store multiple */ |
4055 | trochtova | 97 | if (instr.type == 0x4) |
2464 | jermar | 98 | return true; |
4055 | trochtova | 99 | |
2464 | jermar | 100 | /* oprocessor load/store */ |
4055 | trochtova | 101 | if (instr.type == 0x6) |
2464 | jermar | 102 | return true; |
4055 | trochtova | 103 | |
2464 | jermar | 104 | return false; |
105 | } |
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106 | |||
107 | /** Decides whether the instruction is swap or not. |
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108 | * |
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109 | * @param instr Instruction |
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110 | * |
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111 | * @return true when instruction is swap, false otherwise |
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112 | */ |
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113 | static inline bool is_swap_instruction(instruction_t instr) |
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114 | { |
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115 | /* swap, swapb instruction */ |
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4055 | trochtova | 116 | if ((instr.type == 0x0) && |
117 | ((instr.opcode == 0x8) || (instr.opcode == 0xa)) && |
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118 | (instr.access == 0x0) && (instr.bits567 == 0x4) && (instr.bit4 == 1)) |
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2464 | jermar | 119 | return true; |
4055 | trochtova | 120 | |
2464 | jermar | 121 | return false; |
122 | } |
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123 | |||
124 | /** Decides whether read or write into memory is requested. |
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125 | * |
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126 | * @param instr_addr Address of instruction which tries to access memory. |
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127 | * @param badvaddr Virtual address the instruction tries to access. |
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128 | * |
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129 | * @return Type of access into memory, PF_ACCESS_EXEC if no memory access is |
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130 | * requested. |
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131 | */ |
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132 | static pf_access_t get_memory_access_type(uint32_t instr_addr, |
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133 | uintptr_t badvaddr) |
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134 | { |
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135 | instruction_union_t instr_union; |
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136 | instr_union.pc = instr_addr; |
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137 | |||
138 | instruction_t instr = *(instr_union.instr); |
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139 | |||
140 | /* undefined instructions */ |
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141 | if (instr.condition == 0xf) { |
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4055 | trochtova | 142 | panic("page_fault - instruction does not access memory " |
143 | "(instr_code: %x, badvaddr:%x).", instr, badvaddr); |
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2464 | jermar | 144 | return PF_ACCESS_EXEC; |
145 | } |
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146 | |||
147 | /* load store instructions */ |
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148 | if (is_load_store_instruction(instr)) { |
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149 | if (instr.access == 1) { |
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150 | return PF_ACCESS_READ; |
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151 | } else { |
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152 | return PF_ACCESS_WRITE; |
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153 | } |
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154 | } |
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155 | |||
156 | /* swap, swpb instruction */ |
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157 | if (is_swap_instruction(instr)) { |
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158 | return PF_ACCESS_WRITE; |
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159 | } |
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160 | |||
161 | panic("page_fault - instruction doesn't access memory " |
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4055 | trochtova | 162 | "(instr_code: %x, badvaddr:%x).", instr, badvaddr); |
2464 | jermar | 163 | |
164 | return PF_ACCESS_EXEC; |
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165 | } |
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166 | |||
167 | /** Handles "data abort" exception (load or store at invalid address). |
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168 | * |
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169 | * @param exc_no Exception number. |
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170 | * @param istate CPU state when exception occured. |
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171 | */ |
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172 | void data_abort(int exc_no, istate_t *istate) |
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173 | { |
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2772 | jermar | 174 | fault_status_t fsr __attribute__ ((unused)) = |
175 | read_fault_status_register(); |
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2464 | jermar | 176 | uintptr_t badvaddr = read_fault_address_register(); |
177 | |||
178 | pf_access_t access = get_memory_access_type(istate->pc, badvaddr); |
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179 | |||
180 | int ret = as_page_fault(badvaddr, access, istate); |
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181 | |||
182 | if (ret == AS_PF_FAULT) { |
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183 | print_istate(istate); |
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4156 | trochtova | 184 | printf("page fault - pc: %x, va: %x, status: %x(%x), " |
2464 | jermar | 185 | "access:%d\n", istate->pc, badvaddr, fsr.status, fsr, |
186 | access); |
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4156 | trochtova | 187 | |
4055 | trochtova | 188 | fault_if_from_uspace(istate, "Page fault: %#x.", badvaddr); |
189 | panic("Page fault."); |
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2464 | jermar | 190 | } |
191 | } |
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192 | |||
193 | /** Handles "prefetch abort" exception (instruction couldn't be executed). |
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194 | * |
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195 | * @param exc_no Exception number. |
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196 | * @param istate CPU state when exception occured. |
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197 | */ |
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198 | void prefetch_abort(int exc_no, istate_t *istate) |
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199 | { |
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200 | int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate); |
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201 | |||
202 | if (ret == AS_PF_FAULT) { |
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4156 | trochtova | 203 | printf("prefetch_abort\n"); |
2464 | jermar | 204 | print_istate(istate); |
4055 | trochtova | 205 | panic("page fault - prefetch_abort at address: %x.", |
2464 | jermar | 206 | istate->pc); |
207 | } |
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208 | } |
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209 | |||
210 | /** @} |
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211 | */ |