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| Rev | Author | Line No. | Line |
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| 2362 | jancik | 1 | /* |
| 2 | * Copyright (c) 2007 Petr Stepan, Pavel Jancik |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 29 | /** @addtogroup arm32 |
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| 30 | * @{ |
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| 31 | */ |
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| 32 | /** @file |
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| 2410 | stepan | 33 | * @brief Userspace. |
| 2362 | jancik | 34 | */ |
| 35 | |||
| 36 | #include <userspace.h> |
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| 37 | |||
| 38 | /** Struct to hold general purpose register values */ |
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| 39 | typedef struct { |
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| 40 | uint32_t r0; |
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| 41 | uint32_t r1; |
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| 42 | uint32_t r2; |
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| 43 | uint32_t r3; |
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| 44 | uint32_t r4; |
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| 45 | uint32_t r5; |
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| 46 | uint32_t r6; |
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| 47 | uint32_t r7; |
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| 48 | uint32_t r8; |
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| 49 | uint32_t r9; |
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| 50 | uint32_t r10; |
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| 51 | uint32_t r11; |
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| 52 | uint32_t r12; |
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| 53 | uint32_t sp; |
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| 54 | uint32_t lr; |
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| 55 | uint32_t pc; |
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| 56 | } ustate_t; |
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| 57 | |||
| 2411 | stepan | 58 | |
| 2362 | jancik | 59 | /** Changes processor mode and jumps to the address specified in the first parameter. |
| 60 | * |
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| 61 | * @param kernel_uarg Userspace settings (entry point, stack, ...). |
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| 62 | */ |
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| 63 | void userspace(uspace_arg_t *kernel_uarg) |
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| 64 | { |
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| 65 | |||
| 66 | volatile ustate_t ustate; |
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| 67 | |||
| 68 | // set first parameter |
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| 69 | ustate.r0 = (uintptr_t) kernel_uarg->uspace_uarg; |
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| 70 | |||
| 71 | // clear other registers |
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| 72 | ustate.r1 = ustate.r2 = ustate.r3 = ustate.r4 = |
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| 73 | ustate.r5 = ustate.r6 = ustate.r7 = ustate.r8 = |
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| 74 | ustate.r9 = ustate.r10 = ustate.r11 = ustate.r12 = |
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| 75 | ustate.lr = 0; |
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| 76 | |||
| 77 | //set user stack |
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| 78 | ustate.sp = ((uint32_t)kernel_uarg->uspace_stack) + |
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| 79 | PAGE_SIZE - sizeof(void*); |
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| 80 | |||
| 81 | //set where uspace execution starts |
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| 82 | ustate.pc = (uintptr_t) kernel_uarg->uspace_entry; |
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| 83 | |||
| 84 | //status register in user mode |
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| 85 | ipl_t cpsr = current_status_reg_read(); |
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| 86 | cpsr &= ~STATUS_REG_MODE_MASK | USER_MODE; |
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| 87 | |||
| 88 | ipl_t tmpsr = (cpsr & ~STATUS_REG_MODE_MASK) | SUPERVISOR_MODE; |
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| 89 | |||
| 90 | asm __volatile__ ( |
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| 91 | // save pointer into ustate struct |
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| 92 | "mov r0, %0 \n" |
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| 93 | // save cspr |
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| 94 | "mov r1, %1 \n" |
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| 95 | // change mode into any exception mode |
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| 96 | "msr cpsr_c, %2 \n" |
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| 97 | // set saved cpsr |
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| 98 | "msr spsr_c, r1 \n" |
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| 99 | |||
| 100 | "mov sp, r0 \n" |
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| 101 | // replace almost all registers |
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| 102 | "ldmfd sp!, {r0-r12, sp, lr}^\n" |
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| 103 | //jump to the usermode |
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| 104 | "ldmfd sp!, {pc}^" |
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| 105 | : // no output |
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| 106 | : "r"(&ustate), "r"(cpsr), "r"(tmpsr) // |
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| 107 | : "r0","r1" |
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| 108 | ); |
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| 109 | |||
| 110 | // unreachable |
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| 111 | while(1) ; |
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| 112 | } |
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| 113 | |||
| 114 | |||
| 115 | /** @} |
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| 116 | */ |