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| 2163 | jancik | 1 | /* |
| 2 | * Copyright (c) 2005 Jakub Jermar |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 29 | /** @addtogroup arm32mm |
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| 30 | * @{ |
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| 31 | */ |
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| 32 | /** @file |
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| 33 | */ |
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| 34 | |||
| 35 | #include <mm/tlb.h> |
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| 36 | #include <arch/mm/asid.h> |
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| 37 | #include <arch/asm.h> |
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| 38 | #include <arch/types.h> |
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| 39 | #include <arch/mm/page.h> |
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| 40 | |||
| 41 | /** Invalidate all entries in TLB. */ |
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| 42 | void tlb_invalidate_all(void) |
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| 43 | { |
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| 44 | |||
| 45 | asm volatile ( |
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| 46 | "eor r1, r1\n" |
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| 47 | "MCR p15, 0, r1, c8, c7, 0\n" // see ARM Architecture reference relE 3.7.7 p.528 |
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| 48 | ::: "r1" |
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| 49 | ); |
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| 50 | } |
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| 51 | |||
| 52 | /** Invalidate all entries in TLB that belong to specified address space. |
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| 53 | * |
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| 54 | * @param asid This parameter is ignored as the ARM architecture doesn't support it. |
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| 55 | */ |
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| 56 | void tlb_invalidate_asid(asid_t asid) |
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| 57 | { |
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| 58 | tlb_invalidate_all(); |
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| 59 | } |
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| 60 | |||
| 61 | /** Invalidate single entry in TLB |
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| 62 | * @param page Virtual adress of the page |
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| 63 | */ |
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| 64 | static inline void invlpg(uintptr_t page) |
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| 65 | { |
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| 66 | asm volatile ( |
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| 67 | "MCR p15, 0, %0, c8, c7, 1" |
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| 68 | : /* no output */ |
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| 69 | : "r"(page) /* input */ |
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| 70 | ); |
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| 71 | } |
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| 72 | |||
| 73 | /** Invalidate TLB entries for specified page range belonging to specified address space. |
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| 74 | * |
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| 75 | * @param asid This parameter is ignored as the ARM architecture doesn't support it. |
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| 76 | * @param page Address of the first page whose entry is to be invalidated. |
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| 77 | * @param cnt Number of entries to invalidate. |
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| 78 | */ |
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| 79 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
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| 80 | { |
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| 81 | unsigned int i; |
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| 82 | |||
| 83 | for (i = 0; i < cnt; i++) |
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| 84 | invlpg(page + i * PAGE_SIZE); |
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| 85 | } |
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| 86 | |||
| 87 | /** @} |
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| 88 | */ |