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| Rev | Author | Line No. | Line |
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| 2198 | jancik | 1 | /* |
| 2 | * Copyright (c) 2003-2004 Jakub Jermar |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 29 | /** @addtogroup arm32mm |
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| 30 | * @{ |
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| 31 | */ |
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| 32 | /** @file |
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| 33 | */ |
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| 34 | #include "mm.h" |
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| 35 | |||
| 36 | void init_pte_level0_section_entry( pte_level0_section* pte, unsigned frame){ |
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| 37 | pte->descriptor_type = pte_descriptor_section; |
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| 38 | pte->bufferable = 0; // disable |
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| 39 | pte->cacheable = 0; |
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| 40 | pte->machine_depend = 0; |
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| 41 | pte->domain = 0; |
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| 42 | pte->should_be_zero_1 = 0; |
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| 43 | pte->access_permission = pte_ap_user_no_kernel_rw; |
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| 44 | pte->should_be_zero_2 = 0; |
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| 45 | pte->section_base_addr = (frame << FRAME_WIDTH) >> 20; |
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| 46 | }; |
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| 47 | |||
| 48 | |||
| 49 | // set memory mapping for kernel |
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| 50 | void mm_kernel_mapping(void) { |
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| 51 | int i; |
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| 52 | // Create 1:1 mapping |
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| 53 | for( i=0; i < 4096; i++) |
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| 54 | init_pte_level0_section_entry(&page_table[i+0000], i * FRAMES_PER_SECTION); |
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| 55 | |||
| 56 | // Create Kernel mapping |
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| 57 | const unsigned int offset = ADDR2PFN(PA2KA(0)) / FRAMES_PER_SECTION; |
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| 58 | for( i = offset; i < 4096; i++) |
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| 59 | init_pte_level0_section_entry(&page_table[i], (i - offset) * FRAMES_PER_SECTION); |
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| 60 | |||
| 61 | SET_PTL0_ADDRESS_ARCH( page_table); |
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| 62 | |||
| 63 | // enable paging |
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| 64 | asm volatile ( |
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| 65 | "ldr r0, =0x55555555 \n" |
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| 66 | "mcr p15, 0, r0, c3, c0, 0 \n" //set domain acces rights to client <==> take rights from page tables |
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| 67 | "mrc p15, 0, r0, c1, c0, 0 \n" // get current setting of system ... register 1 isn't only for memmory management |
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| 68 | "ldr r1, =0xFFFFFE8D \n" // mask to disable aligment checks, System, Rom bit disable |
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| 69 | "and r0, r0, r1 \n" |
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| 70 | "ldr r1, =0x00000001 \n" // mask to enable paging |
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| 71 | "orr r0, r0, r1 \n" |
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| 72 | "mcr p15, 0, r0, c1, c0, 0 \n" // store setting |
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| 73 | : |
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| 74 | : |
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| 75 | : "r0", "r1" |
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| 76 | ); |
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| 77 | }; |
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| 78 | |||
| 79 | /** @} |
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| 80 | */ |
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| 81 |