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1 | jermar | 1 | /* |
319 | jermar | 2 | * Copyright (C) 2003-2004 Jakub Jermar |
1 | jermar | 3 | * All rights reserved. |
4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
1705 | cejka | 29 | /** @addtogroup mips32interrupt |
1702 | cejka | 30 | * @{ |
31 | */ |
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32 | /** @file |
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33 | */ |
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34 | |||
575 | palkovsky | 35 | #include <interrupt.h> |
1 | jermar | 36 | #include <arch/interrupt.h> |
37 | #include <arch/types.h> |
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38 | #include <arch.h> |
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39 | #include <arch/cp0.h> |
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40 | #include <time/clock.h> |
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332 | palkovsky | 41 | #include <arch/drivers/arc.h> |
1 | jermar | 42 | |
1258 | palkovsky | 43 | #include <ipc/sysipc.h> |
44 | |||
413 | jermar | 45 | /** Disable interrupts. |
46 | * |
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47 | * @return Old interrupt priority level. |
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48 | */ |
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49 | ipl_t interrupts_disable(void) |
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1 | jermar | 50 | { |
413 | jermar | 51 | ipl_t ipl = (ipl_t) cp0_status_read(); |
52 | cp0_status_write(ipl & ~cp0_status_ie_enabled_bit); |
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53 | return ipl; |
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1 | jermar | 54 | } |
55 | |||
413 | jermar | 56 | /** Enable interrupts. |
57 | * |
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58 | * @return Old interrupt priority level. |
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59 | */ |
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60 | ipl_t interrupts_enable(void) |
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1 | jermar | 61 | { |
413 | jermar | 62 | ipl_t ipl = (ipl_t) cp0_status_read(); |
63 | cp0_status_write(ipl | cp0_status_ie_enabled_bit); |
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64 | return ipl; |
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1 | jermar | 65 | } |
66 | |||
413 | jermar | 67 | /** Restore interrupt priority level. |
68 | * |
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69 | * @param ipl Saved interrupt priority level. |
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70 | */ |
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71 | void interrupts_restore(ipl_t ipl) |
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1 | jermar | 72 | { |
413 | jermar | 73 | cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit)); |
1 | jermar | 74 | } |
75 | |||
413 | jermar | 76 | /** Read interrupt priority level. |
77 | * |
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78 | * @return Current interrupt priority level. |
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79 | */ |
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80 | ipl_t interrupts_read(void) |
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1 | jermar | 81 | { |
125 | jermar | 82 | return cp0_status_read(); |
1 | jermar | 83 | } |
84 | |||
1434 | palkovsky | 85 | /* TODO: This is SMP unsafe!!! */ |
86 | static unsigned long nextcount; |
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87 | /** Start hardware clock */ |
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88 | static void timer_start(void) |
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89 | { |
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90 | nextcount = cp0_compare_value + cp0_count_read(); |
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91 | cp0_compare_write(nextcount); |
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92 | } |
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93 | |||
958 | jermar | 94 | static void timer_exception(int n, istate_t *istate) |
575 | palkovsky | 95 | { |
1434 | palkovsky | 96 | unsigned long drift; |
97 | |||
98 | drift = cp0_count_read() - nextcount; |
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99 | while (drift > cp0_compare_value) { |
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100 | drift -= cp0_compare_value; |
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101 | CPU->missed_clock_ticks++; |
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102 | } |
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103 | nextcount = cp0_count_read() + cp0_compare_value - drift; |
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104 | cp0_compare_write(nextcount); |
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575 | palkovsky | 105 | clock(); |
106 | } |
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107 | |||
958 | jermar | 108 | static void swint0(int n, istate_t *istate) |
575 | palkovsky | 109 | { |
110 | cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */ |
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1258 | palkovsky | 111 | ipc_irq_send_notif(0); |
575 | palkovsky | 112 | } |
113 | |||
958 | jermar | 114 | static void swint1(int n, istate_t *istate) |
575 | palkovsky | 115 | { |
116 | cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */ |
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1258 | palkovsky | 117 | ipc_irq_send_notif(1); |
575 | palkovsky | 118 | } |
119 | |||
120 | /* Initialize basic tables for exception dispatching */ |
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121 | void interrupt_init(void) |
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122 | { |
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590 | palkovsky | 123 | int_register(TIMER_IRQ, "timer", timer_exception); |
124 | int_register(0, "swint0", swint0); |
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125 | int_register(1, "swint1", swint1); |
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1434 | palkovsky | 126 | timer_start(); |
1 | jermar | 127 | } |
1258 | palkovsky | 128 | |
129 | static void ipc_int(int n, istate_t *istate) |
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130 | { |
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131 | ipc_irq_send_notif(n-INT_OFFSET); |
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132 | } |
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133 | |||
134 | /* Reregister irq to be IPC-ready */ |
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1780 | jermar | 135 | void irq_ipc_bind_arch(unative_t irq) |
1258 | palkovsky | 136 | { |
137 | /* Do not allow to redefine timer */ |
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138 | /* Swint0, Swint1 are already handled */ |
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139 | if (irq == TIMER_IRQ || irq < 2) |
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140 | return; |
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141 | int_register(irq, "ipc_int", ipc_int); |
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142 | } |
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1702 | cejka | 143 | |
144 | /** @} |
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145 | */ |
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146 |