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570 | jermar | 1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
29 | #include <arch/mm/tlb.h> |
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30 | #include <mm/tlb.h> |
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619 | jermar | 31 | #include <arch/mm/frame.h> |
32 | #include <arch/mm/page.h> |
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33 | #include <arch/mm/mmu.h> |
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570 | jermar | 34 | #include <print.h> |
617 | jermar | 35 | #include <arch/types.h> |
36 | #include <typedefs.h> |
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619 | jermar | 37 | #include <config.h> |
630 | jermar | 38 | #include <arch/trap/trap.h> |
863 | jermar | 39 | #include <panic.h> |
570 | jermar | 40 | |
619 | jermar | 41 | /** Initialize ITLB and DTLB. |
42 | * |
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43 | * The goal of this function is to disable MMU |
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44 | * so that both TLBs can be purged and new |
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45 | * kernel 4M locked entry can be installed. |
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46 | * After TLB is initialized, MMU is enabled |
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47 | * again. |
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627 | jermar | 48 | * |
49 | * Switching MMU off imposes the requirement for |
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50 | * the kernel to run in identity mapped environment. |
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619 | jermar | 51 | */ |
570 | jermar | 52 | void tlb_arch_init(void) |
53 | { |
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619 | jermar | 54 | tlb_tag_access_reg_t tag; |
55 | tlb_data_t data; |
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56 | frame_address_t fr; |
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57 | page_address_t pg; |
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58 | |||
59 | fr.address = config.base; |
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60 | pg.address = config.base; |
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646 | jermar | 61 | |
619 | jermar | 62 | immu_disable(); |
63 | dmmu_disable(); |
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64 | |||
65 | /* |
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846 | jermar | 66 | * We do identity mapping of 4M-page at 4M. |
619 | jermar | 67 | */ |
68 | tag.value = 0; |
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69 | tag.vpn = pg.vpn; |
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70 | |||
71 | itlb_tag_access_write(tag.value); |
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72 | dtlb_tag_access_write(tag.value); |
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73 | |||
74 | data.value = 0; |
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75 | data.v = true; |
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76 | data.size = PAGESIZE_4M; |
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77 | data.pfn = fr.pfn; |
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78 | data.l = true; |
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79 | data.cp = 1; |
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80 | data.cv = 1; |
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81 | data.p = true; |
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82 | data.w = true; |
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83 | data.g = true; |
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84 | |||
85 | itlb_data_in_write(data.value); |
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86 | dtlb_data_in_write(data.value); |
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87 | |||
627 | jermar | 88 | /* |
89 | * Register window traps can occur before MMU is enabled again. |
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90 | * This ensures that any such traps will be handled from |
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91 | * kernel identity mapped trap handler. |
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92 | */ |
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93 | trap_switch_trap_table(); |
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94 | |||
619 | jermar | 95 | tlb_invalidate_all(); |
96 | |||
97 | dmmu_enable(); |
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98 | immu_enable(); |
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570 | jermar | 99 | } |
100 | |||
863 | jermar | 101 | /** ITLB miss handler. */ |
102 | void fast_instruction_access_mmu_miss(void) |
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103 | { |
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104 | panic("%s\n", __FUNCTION__); |
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105 | } |
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106 | |||
107 | /** DTLB miss handler. */ |
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108 | void fast_data_access_mmu_miss(void) |
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109 | { |
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110 | panic("%s\n", __FUNCTION__); |
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111 | } |
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112 | |||
113 | /** DTLB protection fault handler. */ |
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114 | void fast_data_access_protection(void) |
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115 | { |
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116 | panic("%s\n", __FUNCTION__); |
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117 | } |
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118 | |||
570 | jermar | 119 | /** Print contents of both TLBs. */ |
120 | void tlb_print(void) |
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121 | { |
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122 | int i; |
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123 | tlb_data_t d; |
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124 | tlb_tag_read_reg_t t; |
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125 | |||
126 | printf("I-TLB contents:\n"); |
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127 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
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128 | d.value = itlb_data_access_read(i); |
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613 | jermar | 129 | t.value = itlb_tag_read_read(i); |
570 | jermar | 130 | |
617 | jermar | 131 | printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
132 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
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570 | jermar | 133 | } |
134 | |||
135 | printf("D-TLB contents:\n"); |
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136 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
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137 | d.value = dtlb_data_access_read(i); |
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613 | jermar | 138 | t.value = dtlb_tag_read_read(i); |
570 | jermar | 139 | |
617 | jermar | 140 | printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
141 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
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570 | jermar | 142 | } |
143 | |||
144 | } |
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617 | jermar | 145 | |
146 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
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147 | void tlb_invalidate_all(void) |
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148 | { |
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149 | int i; |
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150 | tlb_data_t d; |
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151 | tlb_tag_read_reg_t t; |
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152 | |||
153 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
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154 | d.value = itlb_data_access_read(i); |
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155 | if (!d.l) { |
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156 | t.value = itlb_tag_read_read(i); |
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157 | d.v = false; |
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158 | itlb_tag_access_write(t.value); |
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159 | itlb_data_access_write(i, d.value); |
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160 | } |
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161 | } |
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162 | |||
163 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
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164 | d.value = dtlb_data_access_read(i); |
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165 | if (!d.l) { |
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166 | t.value = dtlb_tag_read_read(i); |
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167 | d.v = false; |
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168 | dtlb_tag_access_write(t.value); |
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169 | dtlb_data_access_write(i, d.value); |
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170 | } |
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171 | } |
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172 | |||
173 | } |
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174 | |||
175 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context). |
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176 | * |
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177 | * @param asid Address Space ID. |
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178 | */ |
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179 | void tlb_invalidate_asid(asid_t asid) |
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180 | { |
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181 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
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182 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
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183 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
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184 | } |
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185 | |||
727 | jermar | 186 | /** Invalidate all ITLB and DTLB entries for specified page range in specified address space. |
617 | jermar | 187 | * |
188 | * @param asid Address Space ID. |
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727 | jermar | 189 | * @param page First page which to sweep out from ITLB and DTLB. |
190 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
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617 | jermar | 191 | */ |
727 | jermar | 192 | void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt) |
617 | jermar | 193 | { |
727 | jermar | 194 | int i; |
195 | |||
196 | for (i = 0; i < cnt; i++) { |
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197 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
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198 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
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199 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
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200 | } |
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617 | jermar | 201 | } |