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| Rev | Author | Line No. | Line |
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| 162 | decky | 1 | # |
| 2 | # Copyright (C) 2005 Martin Decky |
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| 3 | # All rights reserved. |
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| 4 | # |
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| 5 | # Redistribution and use in source and binary forms, with or without |
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| 6 | # modification, are permitted provided that the following conditions |
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| 7 | # are met: |
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| 8 | # |
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| 9 | # - Redistributions of source code must retain the above copyright |
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| 10 | # notice, this list of conditions and the following disclaimer. |
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| 11 | # - Redistributions in binary form must reproduce the above copyright |
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| 12 | # notice, this list of conditions and the following disclaimer in the |
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| 13 | # documentation and/or other materials provided with the distribution. |
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| 14 | # - The name of the author may not be used to endorse or promote products |
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| 15 | # derived from this software without specific prior written permission. |
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| 16 | # |
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| 17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | # |
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| 28 | |||
| 845 | decky | 29 | #include <arch/asm/regname.h> |
| 191 | decky | 30 | |
| 162 | decky | 31 | .text |
| 32 | |||
| 1220 | decky | 33 | .global userspace_asm |
| 1004 | decky | 34 | .global iret |
| 1277 | decky | 35 | .global iret_syscall |
| 210 | decky | 36 | .global memsetb |
| 37 | .global memcpy |
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| 1288 | jermar | 38 | .global memcpy_from_uspace |
| 39 | .global memcpy_to_uspace |
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| 40 | .global memcpy_from_uspace_failover_address |
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| 41 | .global memcpy_to_uspace_failover_address |
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| 185 | decky | 42 | |
| 1220 | decky | 43 | userspace_asm: |
| 44 | |||
| 45 | # r3 = uspace_uarg |
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| 46 | # r4 = stack |
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| 1267 | decky | 47 | # r5 = entry |
| 48 | |||
| 49 | # disable interrupts |
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| 1220 | decky | 50 | |
| 51 | mfmsr r31 |
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| 52 | rlwinm r31, r31, 0, 17, 15 |
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| 53 | mtmsr r31 |
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| 54 | |||
| 55 | # set entry point |
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| 56 | |||
| 57 | mtsrr0 r5 |
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| 58 | |||
| 59 | # set problem state, enable interrupts |
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| 60 | |||
| 1267 | decky | 61 | ori r31, r31, msr_pr |
| 62 | ori r31, r31, msr_ee |
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| 1220 | decky | 63 | mtsrr1 r31 |
| 64 | |||
| 65 | # set stack |
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| 66 | |||
| 67 | mr sp, r4 |
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| 68 | |||
| 69 | # jump to userspace |
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| 70 | |||
| 71 | rfi |
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| 72 | |||
| 1004 | decky | 73 | iret: |
| 1277 | decky | 74 | |
| 75 | # disable interrupts |
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| 76 | |||
| 77 | mfmsr r31 |
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| 78 | rlwinm r31, r31, 0, 17, 15 |
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| 79 | mtmsr r31 |
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| 80 | |||
| 1004 | decky | 81 | lwz r0, 0(sp) |
| 82 | lwz r2, 4(sp) |
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| 83 | lwz r3, 8(sp) |
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| 84 | lwz r4, 12(sp) |
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| 85 | lwz r5, 16(sp) |
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| 86 | lwz r6, 20(sp) |
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| 87 | lwz r7, 24(sp) |
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| 88 | lwz r8, 28(sp) |
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| 89 | lwz r9, 32(sp) |
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| 90 | lwz r10, 36(sp) |
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| 91 | lwz r11, 40(sp) |
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| 1267 | decky | 92 | lwz r13, 44(sp) |
| 93 | lwz r14, 48(sp) |
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| 94 | lwz r15, 52(sp) |
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| 95 | lwz r16, 56(sp) |
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| 96 | lwz r17, 60(sp) |
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| 97 | lwz r18, 64(sp) |
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| 98 | lwz r19, 68(sp) |
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| 99 | lwz r20, 72(sp) |
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| 100 | lwz r21, 76(sp) |
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| 101 | lwz r22, 80(sp) |
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| 102 | lwz r23, 84(sp) |
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| 103 | lwz r24, 88(sp) |
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| 104 | lwz r25, 92(sp) |
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| 105 | lwz r26, 96(sp) |
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| 106 | lwz r27, 100(sp) |
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| 107 | lwz r28, 104(sp) |
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| 108 | lwz r29, 108(sp) |
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| 109 | lwz r30, 112(sp) |
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| 110 | lwz r31, 116(sp) |
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| 1004 | decky | 111 | |
| 1267 | decky | 112 | lwz r12, 120(sp) |
| 1277 | decky | 113 | mtcr r12 |
| 114 | |||
| 115 | lwz r12, 124(sp) |
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| 1267 | decky | 116 | mtsrr0 r12 |
| 1004 | decky | 117 | |
| 1277 | decky | 118 | lwz r12, 128(sp) |
| 1267 | decky | 119 | mtsrr1 r12 |
| 120 | |||
| 1277 | decky | 121 | lwz r12, 132(sp) |
| 1267 | decky | 122 | mtlr r12 |
| 123 | |||
| 1277 | decky | 124 | lwz r12, 136(sp) |
| 125 | mtctr r12 |
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| 126 | |||
| 127 | lwz r12, 140(sp) |
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| 128 | mtxer r12 |
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| 129 | |||
| 130 | lwz r12, 144(sp) |
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| 131 | lwz sp, 148(sp) |
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| 132 | |||
| 133 | rfi |
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| 134 | |||
| 135 | iret_syscall: |
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| 136 | |||
| 137 | # disable interrupts |
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| 138 | |||
| 139 | mfmsr r31 |
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| 140 | rlwinm r31, r31, 0, 17, 15 |
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| 141 | mtmsr r31 |
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| 142 | |||
| 143 | lwz r0, 0(sp) |
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| 144 | lwz r2, 4(sp) |
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| 145 | lwz r4, 12(sp) |
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| 146 | lwz r5, 16(sp) |
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| 147 | lwz r6, 20(sp) |
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| 148 | lwz r7, 24(sp) |
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| 149 | lwz r8, 28(sp) |
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| 150 | lwz r9, 32(sp) |
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| 151 | lwz r10, 36(sp) |
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| 152 | lwz r11, 40(sp) |
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| 153 | lwz r13, 44(sp) |
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| 154 | lwz r14, 48(sp) |
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| 155 | lwz r15, 52(sp) |
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| 156 | lwz r16, 56(sp) |
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| 157 | lwz r17, 60(sp) |
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| 158 | lwz r18, 64(sp) |
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| 159 | lwz r19, 68(sp) |
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| 160 | lwz r20, 72(sp) |
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| 161 | lwz r21, 76(sp) |
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| 162 | lwz r22, 80(sp) |
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| 163 | lwz r23, 84(sp) |
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| 164 | lwz r24, 88(sp) |
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| 165 | lwz r25, 92(sp) |
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| 166 | lwz r26, 96(sp) |
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| 167 | lwz r27, 100(sp) |
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| 168 | lwz r28, 104(sp) |
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| 169 | lwz r29, 108(sp) |
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| 170 | lwz r30, 112(sp) |
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| 171 | lwz r31, 116(sp) |
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| 172 | |||
| 173 | lwz r12, 120(sp) |
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| 1267 | decky | 174 | mtcr r12 |
| 175 | |||
| 1277 | decky | 176 | lwz r12, 124(sp) |
| 177 | mtsrr0 r12 |
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| 178 | |||
| 179 | lwz r12, 128(sp) |
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| 180 | mtsrr1 r12 |
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| 181 | |||
| 182 | lwz r12, 132(sp) |
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| 183 | mtlr r12 |
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| 184 | |||
| 1267 | decky | 185 | lwz r12, 136(sp) |
| 186 | mtctr r12 |
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| 187 | |||
| 188 | lwz r12, 140(sp) |
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| 189 | mtxer r12 |
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| 1277 | decky | 190 | |
| 191 | lwz r12, 144(sp) |
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| 192 | lwz sp, 148(sp) |
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| 1267 | decky | 193 | |
| 1004 | decky | 194 | rfi |
| 195 | |||
| 210 | decky | 196 | memsetb: |
| 197 | rlwimi r5, r5, 8, 16, 23 |
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| 198 | rlwimi r5, r5, 16, 0, 15 |
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| 199 | |||
| 200 | addi r14, r3, -4 |
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| 201 | |||
| 202 | cmplwi 0, r4, 4 |
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| 203 | blt 7f |
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| 204 | |||
| 205 | stwu r5, 4(r14) |
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| 206 | beqlr |
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| 207 | |||
| 208 | andi. r15, r14, 3 |
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| 209 | add r4, r15, r4 |
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| 210 | subf r14, r15, r14 |
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| 211 | srwi r15, r4, 2 |
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| 212 | mtctr r15 |
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| 213 | |||
| 214 | bdz 6f |
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| 215 | |||
| 216 | 1: |
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| 217 | stwu r5, 4(r14) |
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| 218 | bdnz 1b |
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| 219 | |||
| 220 | 6: |
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| 221 | |||
| 222 | andi. r4, r4, 3 |
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| 223 | |||
| 224 | 7: |
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| 225 | |||
| 226 | cmpwi 0, r4, 0 |
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| 227 | beqlr |
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| 228 | |||
| 229 | mtctr r4 |
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| 230 | addi r6, r6, 3 |
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| 231 | |||
| 232 | 8: |
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| 233 | |||
| 234 | stbu r5, 1(r14) |
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| 235 | bdnz 8b |
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| 236 | |||
| 237 | blr |
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| 238 | |||
| 239 | memcpy: |
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| 1288 | jermar | 240 | memcpy_from_uspace: |
| 241 | memcpy_to_uspace: |
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| 242 | |||
| 860 | decky | 243 | srwi. r7, r5, 3 |
| 244 | addi r6, r3, -4 |
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| 245 | addi r4, r4, -4 |
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| 246 | beq 2f |
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| 247 | |||
| 248 | andi. r0, r6, 3 |
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| 249 | mtctr r7 |
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| 250 | bne 5f |
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| 251 | |||
| 252 | 1: |
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| 253 | |||
| 254 | lwz r7, 4(r4) |
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| 255 | lwzu r8, 8(r4) |
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| 256 | stw r7, 4(r6) |
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| 257 | stwu r8, 8(r6) |
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| 258 | bdnz 1b |
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| 259 | |||
| 260 | andi. r5, r5, 7 |
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| 261 | |||
| 262 | 2: |
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| 263 | |||
| 264 | cmplwi 0, r5, 4 |
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| 265 | blt 3f |
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| 266 | |||
| 267 | lwzu r0, 4(r4) |
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| 268 | addi r5, r5, -4 |
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| 269 | stwu r0, 4(r6) |
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| 270 | |||
| 271 | 3: |
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| 272 | |||
| 273 | cmpwi 0, r5, 0 |
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| 274 | beqlr |
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| 275 | mtctr r5 |
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| 276 | addi r4, r4, 3 |
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| 277 | addi r6, r6, 3 |
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| 278 | |||
| 279 | 4: |
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| 280 | |||
| 281 | lbzu r0, 1(r4) |
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| 282 | stbu r0, 1(r6) |
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| 283 | bdnz 4b |
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| 210 | decky | 284 | blr |
| 860 | decky | 285 | |
| 286 | 5: |
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| 287 | |||
| 288 | subfic r0, r0, 4 |
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| 289 | mtctr r0 |
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| 290 | |||
| 291 | 6: |
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| 292 | |||
| 293 | lbz r7, 4(r4) |
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| 294 | addi r4, r4, 1 |
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| 295 | stb r7, 4(r6) |
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| 296 | addi r6, r6, 1 |
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| 297 | bdnz 6b |
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| 298 | subf r5, r0, r5 |
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| 299 | rlwinm. r7, r5, 32-3, 3, 31 |
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| 300 | beq 2b |
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| 301 | mtctr r7 |
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| 302 | b 1b |
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| 1288 | jermar | 303 | |
| 304 | memcpy_from_uspace_failover_address: |
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| 305 | memcpy_to_uspace_failover_address: |
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| 306 | b memcpy_from_uspace_failover_address |