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173 jermar 1 
/*
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 * Copyright (C) 2005 Martin Decky
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#ifndef __ppc32_ASM_H__
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#define __ppc32_ASM_H__
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#include <arch/types.h>
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#include <config.h>
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/** Enable interrupts.
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 *
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 * Enable interrupts and return previous
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 * value of EE.
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 *
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 * @return Old interrupt priority level.
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 */
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static inline ipl_t interrupts_enable(void) {
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    ipl_t v;
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    ipl_t tmp;
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    __asm__ volatile (
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        "mfmsr %0\n"
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        "mfmsr %1\n"
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        "ori %1, %1, 1 << 15\n"
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        "mtmsr %1\n"
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        : "=r" (v), "=r" (tmp)
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    );
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    return v;
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}
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/** Disable interrupts.
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 *
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 * Disable interrupts and return previous
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 * value of EE.
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 *
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 * @return Old interrupt priority level.
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 */
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static inline ipl_t interrupts_disable(void) {
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    ipl_t v;
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    ipl_t tmp;
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    __asm__ volatile (
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        "mfmsr %0\n"
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        "mfmsr %1\n"
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        "rlwinm %1, %1, 0, 17, 15\n"
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        "mtmsr %1\n"
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        : "=r" (v), "=r" (tmp)
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    );
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    return v;
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}
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/** Restore interrupt priority level.
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 *
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 * Restore EE.
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 *
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 * @param ipl Saved interrupt priority level.
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 */
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static inline void interrupts_restore(ipl_t ipl) {
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    ipl_t tmp;
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    __asm__ volatile (
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        "mfmsr %1\n"
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        "rlwimi  %0, %1, 0, 17, 15\n"
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        "cmpw 0, %0, %1\n"
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        "beq 0f\n"
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        "mtmsr %0\n"
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        "0:\n"
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        : "=r" (ipl), "=r" (tmp)
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        : "0" (ipl)
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    );
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}
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/** Return interrupt priority level.
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 *
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 * Return EE.
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 *
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 * @return Current interrupt priority level.
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 */
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static inline ipl_t interrupts_read(void) {
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    ipl_t v;
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    __asm__ volatile (
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        "mfmsr %0\n"
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        : "=r" (v)
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    );
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    return v;
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}
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/** Return base address of current stack.
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 *
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 * Return the base address of the current stack.
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 * The stack is assumed to be STACK_SIZE bytes long.
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 * The stack must start on page boundary.
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 */
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static inline __address get_stack_base(void)
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{
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    __address v;
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    __asm__ volatile ("and %0, %%r1, %1\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
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    return v;
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}
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void cpu_halt(void);
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void cpu_sleep(void);
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void asm_delay_loop(__u32 t);
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#endif