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| 432 | jermar | 1 | /* |
| 2 | * Copyright (C) 2005 Jakub Jermar |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 29 | #ifndef __ia64_REGISTER_H__ |
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| 30 | #define __ia64_REGISTER_H__ |
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| 31 | |||
| 32 | #define CR_IVR_MASK 0xf |
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| 746 | jermar | 33 | #define PSR_IC_MASK 0x2000 |
| 432 | jermar | 34 | #define PSR_I_MASK 0x4000 |
| 746 | jermar | 35 | #define PSR_PK_MASK 0x8000 |
| 432 | jermar | 36 | |
| 869 | vana | 37 | #define PSR_DT_MASK (1<<17) |
| 38 | #define PSR_RT_MASK (1<<27) |
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| 1023 | vana | 39 | |
| 40 | #define PSR_DFL_MASK (1<<18) |
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| 41 | #define PSR_DFH_MASK (1<<19) |
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| 42 | |||
| 869 | vana | 43 | #define PSR_IT_MASK 0x0000001000000000 |
| 44 | |||
| 912 | jermar | 45 | #define PSR_CPL_SHIFT 32 |
| 46 | #define PSR_CPL_MASK_SHIFTED 3 |
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| 47 | |||
| 919 | jermar | 48 | #define PFM_MASK (~0x3fffffffff) |
| 49 | |||
| 50 | #define RSC_MODE_MASK 3 |
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| 51 | #define RSC_PL_MASK 12 |
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| 52 | |||
| 470 | jermar | 53 | /** Application registers. */ |
| 54 | #define AR_KR0 0 |
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| 55 | #define AR_KR1 1 |
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| 56 | #define AR_KR2 2 |
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| 57 | #define AR_KR3 3 |
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| 58 | #define AR_KR4 4 |
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| 59 | #define AR_KR5 5 |
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| 60 | #define AR_KR6 6 |
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| 61 | #define AR_KR7 7 |
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| 62 | /* AR 8-15 reserved */ |
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| 63 | #define AR_RSC 16 |
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| 64 | #define AR_BSP 17 |
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| 65 | #define AR_BSPSTORE 18 |
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| 66 | #define AR_RNAT 19 |
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| 67 | /* AR 20 reserved */ |
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| 68 | #define AR_FCR 21 |
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| 69 | /* AR 22-23 reserved */ |
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| 70 | #define AR_EFLAG 24 |
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| 71 | #define AR_CSD 25 |
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| 72 | #define AR_SSD 26 |
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| 73 | #define AR_CFLG 27 |
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| 74 | #define AR_FSR 28 |
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| 75 | #define AR_FIR 29 |
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| 76 | #define AR_FDR 30 |
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| 77 | /* AR 31 reserved */ |
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| 78 | #define AR_CCV 32 |
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| 79 | /* AR 33-35 reserved */ |
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| 80 | #define AR_UNAT 36 |
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| 81 | /* AR 37-39 reserved */ |
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| 82 | #define AR_FPSR 40 |
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| 83 | /* AR 41-43 reserved */ |
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| 84 | #define AR_ITC 44 |
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| 85 | /* AR 45-47 reserved */ |
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| 86 | /* AR 48-63 ignored */ |
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| 87 | #define AR_PFS 64 |
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| 88 | #define AR_LC 65 |
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| 89 | #define AR_EC 66 |
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| 90 | /* AR 67-111 reserved */ |
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| 91 | /* AR 112-127 ignored */ |
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| 92 | |||
| 93 | /** Control registers. */ |
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| 94 | #define CR_DCR 0 |
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| 95 | #define CR_ITM 1 |
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| 96 | #define CR_IVA 2 |
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| 97 | /* CR3-CR7 reserved */ |
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| 98 | #define CR_PTA 8 |
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| 99 | /* CR9-CR15 reserved */ |
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| 100 | #define CR_IPSR 16 |
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| 101 | #define CR_ISR 17 |
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| 102 | /* CR18 reserved */ |
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| 103 | #define CR_IIP 19 |
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| 104 | #define CR_IFA 20 |
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| 105 | #define CR_ITIR 21 |
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| 106 | #define CR_IIPA 22 |
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| 107 | #define CR_IFS 23 |
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| 108 | #define CR_IIM 24 |
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| 109 | #define CR_IHA 25 |
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| 110 | /* CR26-CR63 reserved */ |
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| 111 | #define CR_LID 64 |
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| 112 | #define CR_IVR 65 |
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| 113 | #define CR_TPR 66 |
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| 114 | #define CR_EOI 67 |
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| 115 | #define CR_IRR0 68 |
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| 116 | #define CR_IRR1 69 |
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| 117 | #define CR_IRR2 70 |
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| 118 | #define CR_IRR3 71 |
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| 119 | #define CR_ITV 72 |
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| 120 | #define CR_PMV 73 |
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| 121 | #define CR_CMCV 74 |
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| 122 | /* CR75-CR79 reserved */ |
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| 123 | #define CR_LRR0 80 |
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| 124 | #define CR_LRR1 81 |
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| 125 | /* CR82-CR127 reserved */ |
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| 126 | |||
| 472 | jermar | 127 | #ifndef __ASM__ |
| 919 | jermar | 128 | |
| 129 | #include <arch/types.h> |
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| 130 | |||
| 131 | /** Processor Status Register. */ |
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| 132 | union psr { |
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| 133 | __u64 value; |
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| 134 | struct { |
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| 135 | unsigned : 1; |
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| 136 | unsigned be : 1; /**< Big-Endian data accesses. */ |
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| 137 | unsigned up : 1; /**< User Performance monitor enable. */ |
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| 138 | unsigned ac : 1; /**< Alignment Check. */ |
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| 139 | unsigned mfl : 1; /**< Lower floating-point register written. */ |
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| 140 | unsigned mfh : 1; /**< Upper floating-point register written. */ |
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| 141 | unsigned : 7; |
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| 142 | unsigned ic : 1; /**< Interruption Collection. */ |
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| 143 | unsigned i : 1; /**< Interrupt Bit. */ |
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| 144 | unsigned pk : 1; /**< Protection Key enable. */ |
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| 145 | unsigned : 1; |
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| 146 | unsigned dt : 1; /**< Data address Translation. */ |
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| 147 | unsigned dfl : 1; /**< Disabled Floating-point Low register set. */ |
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| 148 | unsigned dfh : 1; /**< Disabled Floating-point High register set. */ |
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| 149 | unsigned sp : 1; /**< Secure Performance monitors. */ |
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| 150 | unsigned pp : 1; /**< Privileged Performance monitor enable. */ |
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| 151 | unsigned di : 1; /**< Disable Instruction set transition. */ |
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| 152 | unsigned si : 1; /**< Secure Interval timer. */ |
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| 153 | unsigned db : 1; /**< Debug Breakpoint fault. */ |
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| 154 | unsigned lp : 1; /**< Lower Privilege transfer trap. */ |
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| 155 | unsigned tb : 1; /**< Taken Branch trap. */ |
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| 156 | unsigned rt : 1; /**< Register Stack Translation. */ |
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| 157 | unsigned : 4; |
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| 158 | unsigned cpl : 2; /**< Current Privilege Level. */ |
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| 159 | unsigned is : 1; /**< Instruction Set. */ |
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| 160 | unsigned mc : 1; /**< Machine Check abort mask. */ |
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| 161 | unsigned it : 1; /**< Instruction address Translation. */ |
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| 162 | unsigned id : 1; /**< Instruction Debug fault disable. */ |
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| 163 | unsigned da : 1; /**< Disable Data Access and Dirty-bit faults. */ |
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| 164 | unsigned dd : 1; /**< Data Debug fault disable. */ |
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| 165 | unsigned ss : 1; /**< Single Step enable. */ |
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| 166 | unsigned ri : 2; /**< Restart Instruction. */ |
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| 167 | unsigned ed : 1; /**< Exception Deferral. */ |
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| 168 | unsigned bn : 1; /**< Register Bank. */ |
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| 169 | unsigned ia : 1; /**< Disable Instruction Access-bit faults. */ |
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| 170 | } __attribute__ ((packed)); |
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| 171 | }; |
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| 172 | typedef union psr psr_t; |
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| 173 | |||
| 174 | /** Register Stack Configuration Register */ |
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| 175 | union rsc { |
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| 176 | __u64 value; |
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| 177 | struct { |
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| 178 | unsigned mode : 2; |
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| 179 | unsigned pl : 2; /**< Privilege Level. */ |
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| 180 | unsigned be : 1; /**< Big-endian. */ |
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| 181 | unsigned : 11; |
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| 182 | unsigned loadrs : 14; |
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| 183 | } __attribute__ ((packed)); |
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| 184 | }; |
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| 185 | typedef union rsc rsc_t; |
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| 186 | |||
| 433 | jermar | 187 | /** External Interrupt Vector Register */ |
| 188 | union cr_ivr { |
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| 189 | __u8 vector; |
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| 190 | __u64 value; |
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| 191 | }; |
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| 192 | |||
| 193 | typedef union cr_ivr cr_ivr_t; |
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| 194 | |||
| 195 | /** Task Priority Register */ |
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| 196 | union cr_tpr { |
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| 197 | struct { |
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| 198 | unsigned : 4; |
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| 199 | unsigned mic: 4; /**< Mask Interrupt Class. */ |
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| 200 | unsigned : 8; |
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| 201 | unsigned mmi: 1; /**< Mask Maskable Interrupts. */ |
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| 202 | } __attribute__ ((packed)); |
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| 203 | __u64 value; |
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| 204 | }; |
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| 205 | |||
| 206 | typedef union cr_tpr cr_tpr_t; |
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| 207 | |||
| 208 | /** Interval Timer Vector */ |
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| 209 | union cr_itv { |
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| 210 | struct { |
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| 211 | unsigned vector : 8; |
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| 212 | unsigned : 4; |
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| 213 | unsigned : 1; |
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| 214 | unsigned : 3; |
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| 215 | unsigned m : 1; /**< Mask. */ |
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| 216 | } __attribute__ ((packed)); |
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| 217 | __u64 value; |
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| 218 | }; |
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| 219 | |||
| 220 | typedef union cr_itv cr_itv_t; |
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| 221 | |||
| 472 | jermar | 222 | /** Interruption Status Register */ |
| 223 | union cr_isr { |
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| 224 | struct { |
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| 225 | union { |
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| 226 | /** General Exception code field structuring. */ |
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| 227 | struct { |
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| 228 | unsigned ge_na : 4; |
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| 229 | unsigned ge_code : 4; |
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| 230 | } __attribute__ ((packed)); |
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| 231 | __u16 code; |
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| 232 | }; |
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| 233 | __u8 vector; |
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| 234 | unsigned : 8; |
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| 235 | unsigned x : 1; /**< Execute exception. */ |
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| 236 | unsigned w : 1; /**< Write exception. */ |
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| 237 | unsigned r : 1; /**< Read exception. */ |
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| 238 | unsigned na : 1; /**< Non-access exception. */ |
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| 239 | unsigned sp : 1; /**< Speculative load exception. */ |
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| 240 | unsigned rs : 1; /**< Register stack. */ |
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| 241 | unsigned ir : 1; /**< Incomplete Register frame. */ |
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| 242 | unsigned ni : 1; /**< Nested Interruption. */ |
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| 243 | unsigned so : 1; /**< IA-32 Supervisor Override. */ |
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| 244 | unsigned ei : 2; /**< Excepting Instruction. */ |
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| 245 | unsigned ed : 1; /**< Exception Deferral. */ |
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| 246 | unsigned : 20; |
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| 247 | } __attribute__ ((packed)); |
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| 248 | __u64 value; |
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| 249 | }; |
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| 250 | |||
| 251 | typedef union cr_isr cr_isr_t; |
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| 252 | |||
| 476 | jermar | 253 | /** CPUID Register 3 */ |
| 254 | union cpuid3 { |
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| 255 | struct { |
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| 256 | __u8 number; |
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| 257 | __u8 revision; |
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| 258 | __u8 model; |
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| 259 | __u8 family; |
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| 260 | __u8 archrev; |
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| 261 | } __attribute__ ((packed)); |
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| 262 | __u64 value; |
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| 263 | }; |
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| 264 | |||
| 265 | typedef union cpuid3 cpuid3_t; |
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| 266 | |||
| 472 | jermar | 267 | #endif /* !__ASM__ */ |
| 268 | |||
| 432 | jermar | 269 | #endif |