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| 1 | jermar | 1 | /* |
| 2 | * Copyright (C) 2001-2004 Jakub Jermar |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 29 | #ifndef __APIC_H__ |
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| 30 | #define __APIC_H__ |
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| 31 | |||
| 32 | #include <arch/types.h> |
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| 33 | #include <cpu.h> |
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| 34 | |||
| 35 | #define FIXED (0<<0) |
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| 36 | #define LOPRI (1<<0) |
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| 37 | |||
| 515 | jermar | 38 | #define APIC_ID_COUNT 16 |
| 39 | |||
| 1 | jermar | 40 | /* local APIC macros */ |
| 41 | #define IPI_INIT 0 |
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| 42 | #define IPI_STARTUP 0 |
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| 43 | |||
| 513 | jermar | 44 | /** Delivery modes. */ |
| 45 | #define DELMOD_FIXED 0x0 |
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| 46 | #define DELMOD_LOWPRI 0x1 |
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| 47 | #define DELMOD_SMI 0x2 |
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| 48 | /* 0x3 reserved */ |
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| 49 | #define DELMOD_NMI 0x4 |
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| 50 | #define DELMOD_INIT 0x5 |
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| 51 | #define DELMOD_STARTUP 0x6 |
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| 52 | #define DELMOD_EXTINT 0x7 |
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| 1 | jermar | 53 | |
| 513 | jermar | 54 | /** Destination modes. */ |
| 55 | #define DESTMOD_PHYS 0x0 |
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| 56 | #define DESTMOD_LOGIC 0x1 |
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| 57 | |||
| 58 | /** Trigger Modes. */ |
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| 59 | #define TRIGMOD_EDGE 0x0 |
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| 60 | #define TRIGMOD_LEVEL 0x1 |
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| 61 | |||
| 62 | /** Levels. */ |
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| 63 | #define LEVEL_DEASSERT 0x0 |
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| 64 | #define LEVEL_ASSERT 0x1 |
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| 65 | |||
| 66 | /** Destination Shorthands. */ |
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| 67 | #define SHORTHAND_NONE 0x0 |
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| 68 | #define SHORTHAND_SELF 0x1 |
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| 69 | #define SHORTHAND_ALL_INCL 0x2 |
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| 70 | #define SHORTHAND_ALL_EXCL 0x3 |
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| 71 | |||
| 72 | /** Interrupt Input Pin Polarities. */ |
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| 73 | #define POLARITY_HIGH 0x0 |
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| 74 | #define POLARITY_LOW 0x1 |
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| 75 | |||
| 514 | jermar | 76 | /** Divide Values. (Bit 2 is always 0) */ |
| 77 | #define DIVIDE_2 0x0 |
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| 78 | #define DIVIDE_4 0x1 |
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| 79 | #define DIVIDE_8 0x2 |
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| 80 | #define DIVIDE_16 0x3 |
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| 81 | #define DIVIDE_32 0x8 |
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| 82 | #define DIVIDE_64 0x9 |
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| 83 | #define DIVIDE_128 0xa |
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| 84 | #define DIVIDE_1 0xb |
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| 85 | |||
| 86 | /** Timer Modes. */ |
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| 87 | #define TIMER_ONESHOT 0x0 |
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| 88 | #define TIMER_PERIODIC 0x1 |
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| 89 | |||
| 515 | jermar | 90 | /** Delivery status. */ |
| 91 | #define DELIVS_IDLE 0x0 |
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| 92 | #define DELIVS_PENDING 0x1 |
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| 1 | jermar | 93 | |
| 515 | jermar | 94 | /** Destination masks. */ |
| 95 | #define DEST_ALL 0xff |
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| 96 | |||
| 672 | jermar | 97 | /** Dest format models. */ |
| 98 | #define MODEL_FLAT 0xf |
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| 99 | #define MODEL_CLUSTER 0x0 |
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| 100 | |||
| 513 | jermar | 101 | /** Interrupt Command Register. */ |
| 1 | jermar | 102 | #define ICRlo (0x300/sizeof(__u32)) |
| 103 | #define ICRhi (0x310/sizeof(__u32)) |
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| 513 | jermar | 104 | struct icr { |
| 105 | union { |
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| 106 | __u32 lo; |
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| 107 | struct { |
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| 108 | __u8 vector; /**< Interrupt Vector. */ |
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| 109 | unsigned delmod : 3; /**< Delivery Mode. */ |
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| 110 | unsigned destmod : 1; /**< Destination Mode. */ |
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| 111 | unsigned delivs : 1; /**< Delivery status (RO). */ |
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| 112 | unsigned : 1; /**< Reserved. */ |
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| 113 | unsigned level : 1; /**< Level. */ |
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| 114 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
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| 115 | unsigned : 2; /**< Reserved. */ |
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| 116 | unsigned shorthand : 2; /**< Destination Shorthand. */ |
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| 117 | unsigned : 12; /**< Reserved. */ |
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| 118 | } __attribute__ ((packed)); |
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| 119 | }; |
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| 120 | union { |
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| 121 | __u32 hi; |
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| 122 | struct { |
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| 123 | unsigned : 24; /**< Reserved. */ |
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| 124 | __u8 dest; /**< Destination field. */ |
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| 125 | } __attribute__ ((packed)); |
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| 126 | }; |
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| 127 | } __attribute__ ((packed)); |
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| 128 | typedef struct icr icr_t; |
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| 1 | jermar | 129 | |
| 130 | /* End Of Interrupt */ |
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| 131 | #define EOI (0x0b0/sizeof(__u32)) |
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| 132 | |||
| 514 | jermar | 133 | /** Error Status Register. */ |
| 1 | jermar | 134 | #define ESR (0x280/sizeof(__u32)) |
| 514 | jermar | 135 | union esr { |
| 136 | __u32 value; |
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| 137 | __u8 err_bitmap; |
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| 138 | struct { |
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| 139 | unsigned send_checksum_error : 1; |
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| 140 | unsigned receive_checksum_error : 1; |
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| 141 | unsigned send_accept_error : 1; |
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| 142 | unsigned receive_accept_error : 1; |
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| 143 | unsigned : 1; |
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| 144 | unsigned send_illegal_vector : 1; |
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| 145 | unsigned received_illegal_vector : 1; |
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| 146 | unsigned illegal_register_address : 1; |
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| 147 | unsigned : 24; |
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| 148 | } __attribute__ ((packed)); |
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| 149 | }; |
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| 150 | typedef union esr esr_t; |
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| 1 | jermar | 151 | |
| 152 | /* Task Priority Register */ |
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| 153 | #define TPR (0x080/sizeof(__u32)) |
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| 154 | #define TPRClear 0xffffff00 |
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| 155 | |||
| 513 | jermar | 156 | /** Spurious-Interrupt Vector Register. */ |
| 1 | jermar | 157 | #define SVR (0x0f0/sizeof(__u32)) |
| 513 | jermar | 158 | union svr { |
| 159 | __u32 value; |
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| 160 | struct { |
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| 161 | __u8 vector; /**< Spurious Vector */ |
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| 162 | unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable */ |
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| 163 | unsigned focus_checking : 1; /**< Focus Processor Checking */ |
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| 164 | unsigned : 22; /**< Reserved. */ |
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| 165 | } __attribute__ ((packed)); |
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| 166 | }; |
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| 167 | typedef union svr svr_t; |
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| 1 | jermar | 168 | |
| 514 | jermar | 169 | /** Time Divide Configuration Register. */ |
| 1 | jermar | 170 | #define TDCR (0x3e0/sizeof(__u32)) |
| 514 | jermar | 171 | union tdcr { |
| 172 | __u32 value; |
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| 173 | struct { |
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| 174 | unsigned div_value : 4; /**< Divide Value, bit 2 is always 0. */ |
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| 175 | unsigned : 28; /**< Reserved. */ |
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| 176 | } __attribute__ ((packed)); |
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| 177 | }; |
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| 178 | typedef union tdcr tdcr_t; |
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| 1 | jermar | 179 | |
| 180 | /* Initial Count Register for Timer */ |
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| 181 | #define ICRT (0x380/sizeof(__u32)) |
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| 182 | |||
| 183 | /* Current Count Register for Timer */ |
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| 184 | #define CCRT (0x390/sizeof(__u32)) |
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| 185 | |||
| 513 | jermar | 186 | /** LVT Timer register. */ |
| 1 | jermar | 187 | #define LVT_Tm (0x320/sizeof(__u32)) |
| 513 | jermar | 188 | union lvt_tm { |
| 189 | __u32 value; |
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| 190 | struct { |
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| 191 | __u8 vector; /**< Local Timer Interrupt vector. */ |
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| 192 | unsigned : 4; /**< Reserved. */ |
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| 193 | unsigned delivs : 1; /**< Delivery status (RO). */ |
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| 194 | unsigned : 3; /**< Reserved. */ |
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| 195 | unsigned masked : 1; /**< Interrupt Mask. */ |
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| 196 | unsigned mode : 1; /**< Timer Mode. */ |
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| 197 | unsigned : 14; /**< Reserved. */ |
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| 198 | } __attribute__ ((packed)); |
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| 199 | }; |
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| 200 | typedef union lvt_tm lvt_tm_t; |
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| 201 | |||
| 202 | /** LVT LINT registers. */ |
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| 1 | jermar | 203 | #define LVT_LINT0 (0x350/sizeof(__u32)) |
| 204 | #define LVT_LINT1 (0x360/sizeof(__u32)) |
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| 513 | jermar | 205 | union lvt_lint { |
| 206 | __u32 value; |
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| 207 | struct { |
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| 208 | __u8 vector; /**< LINT Interrupt vector. */ |
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| 209 | unsigned delmod : 3; /**< Delivery Mode. */ |
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| 210 | unsigned : 1; /**< Reserved. */ |
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| 211 | unsigned delivs : 1; /**< Delivery status (RO). */ |
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| 212 | unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ |
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| 213 | unsigned irr : 1; /**< Remote IRR (RO). */ |
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| 214 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
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| 215 | unsigned masked : 1; /**< Interrupt Mask. */ |
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| 216 | unsigned : 15; /**< Reserved. */ |
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| 217 | } __attribute__ ((packed)); |
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| 218 | }; |
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| 219 | typedef union lvt_lint lvt_lint_t; |
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| 220 | |||
| 221 | /** LVT Error register. */ |
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| 1 | jermar | 222 | #define LVT_Err (0x370/sizeof(__u32)) |
| 513 | jermar | 223 | union lvt_error { |
| 224 | __u32 value; |
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| 225 | struct { |
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| 226 | __u8 vector; /**< Local Timer Interrupt vector. */ |
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| 227 | unsigned : 4; /**< Reserved. */ |
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| 228 | unsigned delivs : 1; /**< Delivery status (RO). */ |
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| 229 | unsigned : 3; /**< Reserved. */ |
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| 230 | unsigned masked : 1; /**< Interrupt Mask. */ |
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| 231 | unsigned : 15; /**< Reserved. */ |
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| 232 | } __attribute__ ((packed)); |
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| 233 | }; |
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| 234 | typedef union lvt_error lvt_error_t; |
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| 235 | |||
| 514 | jermar | 236 | /** Local APIC ID Register. */ |
| 1 | jermar | 237 | #define L_APIC_ID (0x020/sizeof(__u32)) |
| 515 | jermar | 238 | union l_apic_id { |
| 514 | jermar | 239 | __u32 value; |
| 240 | struct { |
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| 241 | unsigned : 24; /**< Reserved. */ |
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| 242 | __u8 apic_id; /**< Local APIC ID. */ |
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| 243 | } __attribute__ ((packed)); |
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| 244 | }; |
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| 515 | jermar | 245 | typedef union l_apic_id l_apic_id_t; |
| 1 | jermar | 246 | |
| 27 | jermar | 247 | /* Local APIC Version Register */ |
| 248 | #define LAVR (0x030/sizeof(__u32)) |
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| 249 | #define LAVR_Mask 0xff |
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| 250 | #define is_local_apic(x) (((x)&LAVR_Mask&0xf0)==0x1) |
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| 251 | #define is_82489DX_apic(x) ((((x)&LAVR_Mask&0xf0)==0x0)) |
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| 252 | #define is_local_xapic(x) (((x)&LAVR_Mask)==0x14) |
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| 253 | |||
| 672 | jermar | 254 | /** Logical Destination Register. */ |
| 255 | #define LDR (0x0d0/sizeof(__u32)) |
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| 256 | union ldr { |
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| 257 | __u32 value; |
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| 258 | struct { |
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| 259 | unsigned : 24; /**< Reserver. */ |
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| 260 | __u8 id; /**< Logical APIC ID. */ |
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| 261 | } __attribute__ ((packed)); |
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| 262 | }; |
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| 263 | typedef union ldr ldr_t; |
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| 264 | |||
| 265 | /** Destination Format Register. */ |
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| 266 | #define DFR (0x0e0/sizeof(__u32)) |
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| 267 | union dfr { |
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| 268 | __u32 value; |
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| 269 | struct { |
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| 270 | unsigned : 28; /**< Reserved, all ones. */ |
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| 271 | unsigned model : 4; /**< Model. */ |
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| 272 | } __attribute__ ((packed)); |
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| 273 | }; |
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| 274 | typedef union dfr dfr_t; |
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| 275 | |||
| 1 | jermar | 276 | /* IO APIC */ |
| 277 | #define IOREGSEL (0x00/sizeof(__u32)) |
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| 278 | #define IOWIN (0x10/sizeof(__u32)) |
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| 279 | |||
| 280 | #define IOAPICID 0x00 |
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| 281 | #define IOAPICVER 0x01 |
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| 282 | #define IOAPICARB 0x02 |
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| 283 | #define IOREDTBL 0x10 |
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| 284 | |||
| 514 | jermar | 285 | /** I/O Register Select Register. */ |
| 286 | union io_regsel { |
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| 287 | __u32 value; |
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| 288 | struct { |
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| 289 | __u8 reg_addr; /**< APIC Register Address. */ |
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| 290 | unsigned : 24; /**< Reserved. */ |
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| 291 | } __attribute__ ((packed)); |
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| 292 | }; |
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| 293 | typedef union io_regsel io_regsel_t; |
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| 294 | |||
| 512 | jermar | 295 | /** I/O Redirection Register. */ |
| 296 | struct io_redirection_reg { |
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| 297 | union { |
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| 298 | __u32 lo; |
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| 299 | struct { |
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| 513 | jermar | 300 | __u8 intvec; /**< Interrupt Vector. */ |
| 512 | jermar | 301 | unsigned delmod : 3; /**< Delivery Mode. */ |
| 302 | unsigned destmod : 1; /**< Destination mode. */ |
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| 303 | unsigned delivs : 1; /**< Delivery status (RO). */ |
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| 304 | unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ |
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| 305 | unsigned irr : 1; /**< Remote IRR (RO). */ |
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| 306 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
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| 307 | unsigned masked : 1; /**< Interrupt Mask. */ |
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| 308 | unsigned : 15; /**< Reserved. */ |
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| 513 | jermar | 309 | } __attribute__ ((packed)); |
| 512 | jermar | 310 | }; |
| 311 | union { |
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| 312 | __u32 hi; |
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| 313 | struct { |
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| 314 | unsigned : 24; /**< Reserved. */ |
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| 513 | jermar | 315 | __u8 dest : 8; /**< Destination Field. */ |
| 316 | } __attribute__ ((packed)); |
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| 512 | jermar | 317 | }; |
| 318 | |||
| 319 | } __attribute__ ((packed)); |
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| 320 | typedef struct io_redirection_reg io_redirection_reg_t; |
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| 321 | |||
| 515 | jermar | 322 | |
| 323 | /** IO APIC Identification Register. */ |
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| 324 | union io_apic_id { |
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| 325 | __u32 value; |
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| 326 | struct { |
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| 327 | unsigned : 24; /**< Reserved. */ |
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| 328 | unsigned apic_id : 4; /**< IO APIC ID. */ |
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| 329 | unsigned : 4; /**< Reserved. */ |
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| 330 | } __attribute__ ((packed)); |
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| 331 | }; |
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| 332 | typedef union io_apic_id io_apic_id_t; |
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| 333 | |||
| 1 | jermar | 334 | extern volatile __u32 *l_apic; |
| 335 | extern volatile __u32 *io_apic; |
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| 336 | |||
| 337 | extern __u32 apic_id_mask; |
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| 338 | |||
| 339 | extern void apic_init(void); |
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| 340 | |||
| 341 | extern void l_apic_init(void); |
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| 342 | extern void l_apic_eoi(void); |
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| 5 | jermar | 343 | extern int l_apic_broadcast_custom_ipi(__u8 vector); |
| 1 | jermar | 344 | extern int l_apic_send_init_ipi(__u8 apicid); |
| 345 | extern void l_apic_debug(void); |
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| 81 | jermar | 346 | extern __u8 l_apic_id(void); |
| 1 | jermar | 347 | |
| 348 | extern __u32 io_apic_read(__u8 address); |
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| 349 | extern void io_apic_write(__u8 address , __u32 x); |
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| 514 | jermar | 350 | extern void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags); |
| 1 | jermar | 351 | extern void io_apic_disable_irqs(__u16 irqmask); |
| 352 | extern void io_apic_enable_irqs(__u16 irqmask); |
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| 353 | |||
| 354 | #endif |