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| 1 | jermar | 1 | /* |
| 2 | * Copyright (C) 2001-2004 Jakub Jermar |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 1702 | cejka | 29 | /** @addtogroup ia32 |
| 30 | * @{ |
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| 31 | */ |
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| 32 | /** @file |
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| 33 | */ |
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| 34 | |||
| 1 | jermar | 35 | #ifndef __APIC_H__ |
| 36 | #define __APIC_H__ |
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| 37 | |||
| 38 | #include <arch/types.h> |
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| 39 | #include <cpu.h> |
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| 40 | |||
| 41 | #define FIXED (0<<0) |
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| 42 | #define LOPRI (1<<0) |
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| 43 | |||
| 515 | jermar | 44 | #define APIC_ID_COUNT 16 |
| 45 | |||
| 1 | jermar | 46 | /* local APIC macros */ |
| 47 | #define IPI_INIT 0 |
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| 48 | #define IPI_STARTUP 0 |
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| 49 | |||
| 513 | jermar | 50 | /** Delivery modes. */ |
| 51 | #define DELMOD_FIXED 0x0 |
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| 52 | #define DELMOD_LOWPRI 0x1 |
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| 53 | #define DELMOD_SMI 0x2 |
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| 54 | /* 0x3 reserved */ |
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| 55 | #define DELMOD_NMI 0x4 |
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| 56 | #define DELMOD_INIT 0x5 |
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| 57 | #define DELMOD_STARTUP 0x6 |
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| 58 | #define DELMOD_EXTINT 0x7 |
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| 1 | jermar | 59 | |
| 513 | jermar | 60 | /** Destination modes. */ |
| 61 | #define DESTMOD_PHYS 0x0 |
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| 62 | #define DESTMOD_LOGIC 0x1 |
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| 63 | |||
| 64 | /** Trigger Modes. */ |
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| 65 | #define TRIGMOD_EDGE 0x0 |
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| 66 | #define TRIGMOD_LEVEL 0x1 |
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| 67 | |||
| 68 | /** Levels. */ |
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| 69 | #define LEVEL_DEASSERT 0x0 |
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| 70 | #define LEVEL_ASSERT 0x1 |
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| 71 | |||
| 72 | /** Destination Shorthands. */ |
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| 73 | #define SHORTHAND_NONE 0x0 |
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| 74 | #define SHORTHAND_SELF 0x1 |
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| 75 | #define SHORTHAND_ALL_INCL 0x2 |
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| 76 | #define SHORTHAND_ALL_EXCL 0x3 |
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| 77 | |||
| 78 | /** Interrupt Input Pin Polarities. */ |
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| 79 | #define POLARITY_HIGH 0x0 |
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| 80 | #define POLARITY_LOW 0x1 |
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| 81 | |||
| 514 | jermar | 82 | /** Divide Values. (Bit 2 is always 0) */ |
| 83 | #define DIVIDE_2 0x0 |
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| 84 | #define DIVIDE_4 0x1 |
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| 85 | #define DIVIDE_8 0x2 |
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| 86 | #define DIVIDE_16 0x3 |
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| 87 | #define DIVIDE_32 0x8 |
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| 88 | #define DIVIDE_64 0x9 |
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| 89 | #define DIVIDE_128 0xa |
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| 90 | #define DIVIDE_1 0xb |
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| 91 | |||
| 92 | /** Timer Modes. */ |
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| 93 | #define TIMER_ONESHOT 0x0 |
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| 94 | #define TIMER_PERIODIC 0x1 |
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| 95 | |||
| 515 | jermar | 96 | /** Delivery status. */ |
| 97 | #define DELIVS_IDLE 0x0 |
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| 98 | #define DELIVS_PENDING 0x1 |
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| 1 | jermar | 99 | |
| 515 | jermar | 100 | /** Destination masks. */ |
| 101 | #define DEST_ALL 0xff |
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| 102 | |||
| 672 | jermar | 103 | /** Dest format models. */ |
| 104 | #define MODEL_FLAT 0xf |
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| 105 | #define MODEL_CLUSTER 0x0 |
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| 106 | |||
| 513 | jermar | 107 | /** Interrupt Command Register. */ |
| 1 | jermar | 108 | #define ICRlo (0x300/sizeof(__u32)) |
| 109 | #define ICRhi (0x310/sizeof(__u32)) |
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| 513 | jermar | 110 | struct icr { |
| 111 | union { |
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| 112 | __u32 lo; |
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| 113 | struct { |
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| 114 | __u8 vector; /**< Interrupt Vector. */ |
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| 115 | unsigned delmod : 3; /**< Delivery Mode. */ |
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| 116 | unsigned destmod : 1; /**< Destination Mode. */ |
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| 117 | unsigned delivs : 1; /**< Delivery status (RO). */ |
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| 118 | unsigned : 1; /**< Reserved. */ |
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| 119 | unsigned level : 1; /**< Level. */ |
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| 120 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
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| 121 | unsigned : 2; /**< Reserved. */ |
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| 122 | unsigned shorthand : 2; /**< Destination Shorthand. */ |
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| 123 | unsigned : 12; /**< Reserved. */ |
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| 124 | } __attribute__ ((packed)); |
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| 125 | }; |
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| 126 | union { |
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| 127 | __u32 hi; |
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| 128 | struct { |
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| 129 | unsigned : 24; /**< Reserved. */ |
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| 130 | __u8 dest; /**< Destination field. */ |
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| 131 | } __attribute__ ((packed)); |
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| 132 | }; |
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| 133 | } __attribute__ ((packed)); |
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| 134 | typedef struct icr icr_t; |
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| 1 | jermar | 135 | |
| 1251 | jermar | 136 | /* End Of Interrupt. */ |
| 1 | jermar | 137 | #define EOI (0x0b0/sizeof(__u32)) |
| 138 | |||
| 514 | jermar | 139 | /** Error Status Register. */ |
| 1 | jermar | 140 | #define ESR (0x280/sizeof(__u32)) |
| 514 | jermar | 141 | union esr { |
| 142 | __u32 value; |
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| 143 | __u8 err_bitmap; |
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| 144 | struct { |
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| 145 | unsigned send_checksum_error : 1; |
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| 146 | unsigned receive_checksum_error : 1; |
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| 147 | unsigned send_accept_error : 1; |
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| 148 | unsigned receive_accept_error : 1; |
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| 149 | unsigned : 1; |
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| 150 | unsigned send_illegal_vector : 1; |
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| 151 | unsigned received_illegal_vector : 1; |
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| 152 | unsigned illegal_register_address : 1; |
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| 153 | unsigned : 24; |
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| 154 | } __attribute__ ((packed)); |
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| 155 | }; |
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| 156 | typedef union esr esr_t; |
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| 1 | jermar | 157 | |
| 158 | /* Task Priority Register */ |
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| 159 | #define TPR (0x080/sizeof(__u32)) |
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| 750 | jermar | 160 | union tpr { |
| 161 | __u32 value; |
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| 162 | struct { |
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| 163 | unsigned pri_sc : 4; /**< Task Priority Sub-Class. */ |
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| 164 | unsigned pri : 4; /**< Task Priority. */ |
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| 165 | } __attribute__ ((packed)); |
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| 166 | }; |
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| 167 | typedef union tpr tpr_t; |
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| 1 | jermar | 168 | |
| 513 | jermar | 169 | /** Spurious-Interrupt Vector Register. */ |
| 1 | jermar | 170 | #define SVR (0x0f0/sizeof(__u32)) |
| 513 | jermar | 171 | union svr { |
| 172 | __u32 value; |
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| 173 | struct { |
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| 750 | jermar | 174 | __u8 vector; /**< Spurious Vector. */ |
| 175 | unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable. */ |
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| 176 | unsigned focus_checking : 1; /**< Focus Processor Checking. */ |
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| 513 | jermar | 177 | unsigned : 22; /**< Reserved. */ |
| 178 | } __attribute__ ((packed)); |
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| 179 | }; |
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| 180 | typedef union svr svr_t; |
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| 1 | jermar | 181 | |
| 514 | jermar | 182 | /** Time Divide Configuration Register. */ |
| 1 | jermar | 183 | #define TDCR (0x3e0/sizeof(__u32)) |
| 514 | jermar | 184 | union tdcr { |
| 185 | __u32 value; |
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| 186 | struct { |
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| 187 | unsigned div_value : 4; /**< Divide Value, bit 2 is always 0. */ |
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| 188 | unsigned : 28; /**< Reserved. */ |
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| 189 | } __attribute__ ((packed)); |
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| 190 | }; |
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| 191 | typedef union tdcr tdcr_t; |
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| 1 | jermar | 192 | |
| 193 | /* Initial Count Register for Timer */ |
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| 194 | #define ICRT (0x380/sizeof(__u32)) |
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| 195 | |||
| 196 | /* Current Count Register for Timer */ |
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| 197 | #define CCRT (0x390/sizeof(__u32)) |
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| 198 | |||
| 513 | jermar | 199 | /** LVT Timer register. */ |
| 1 | jermar | 200 | #define LVT_Tm (0x320/sizeof(__u32)) |
| 513 | jermar | 201 | union lvt_tm { |
| 202 | __u32 value; |
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| 203 | struct { |
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| 204 | __u8 vector; /**< Local Timer Interrupt vector. */ |
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| 205 | unsigned : 4; /**< Reserved. */ |
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| 206 | unsigned delivs : 1; /**< Delivery status (RO). */ |
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| 207 | unsigned : 3; /**< Reserved. */ |
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| 208 | unsigned masked : 1; /**< Interrupt Mask. */ |
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| 209 | unsigned mode : 1; /**< Timer Mode. */ |
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| 210 | unsigned : 14; /**< Reserved. */ |
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| 211 | } __attribute__ ((packed)); |
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| 212 | }; |
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| 213 | typedef union lvt_tm lvt_tm_t; |
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| 214 | |||
| 215 | /** LVT LINT registers. */ |
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| 1 | jermar | 216 | #define LVT_LINT0 (0x350/sizeof(__u32)) |
| 217 | #define LVT_LINT1 (0x360/sizeof(__u32)) |
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| 513 | jermar | 218 | union lvt_lint { |
| 219 | __u32 value; |
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| 220 | struct { |
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| 221 | __u8 vector; /**< LINT Interrupt vector. */ |
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| 222 | unsigned delmod : 3; /**< Delivery Mode. */ |
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| 223 | unsigned : 1; /**< Reserved. */ |
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| 224 | unsigned delivs : 1; /**< Delivery status (RO). */ |
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| 225 | unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ |
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| 226 | unsigned irr : 1; /**< Remote IRR (RO). */ |
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| 227 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
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| 228 | unsigned masked : 1; /**< Interrupt Mask. */ |
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| 229 | unsigned : 15; /**< Reserved. */ |
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| 230 | } __attribute__ ((packed)); |
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| 231 | }; |
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| 232 | typedef union lvt_lint lvt_lint_t; |
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| 233 | |||
| 234 | /** LVT Error register. */ |
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| 1 | jermar | 235 | #define LVT_Err (0x370/sizeof(__u32)) |
| 513 | jermar | 236 | union lvt_error { |
| 237 | __u32 value; |
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| 238 | struct { |
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| 239 | __u8 vector; /**< Local Timer Interrupt vector. */ |
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| 240 | unsigned : 4; /**< Reserved. */ |
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| 241 | unsigned delivs : 1; /**< Delivery status (RO). */ |
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| 242 | unsigned : 3; /**< Reserved. */ |
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| 243 | unsigned masked : 1; /**< Interrupt Mask. */ |
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| 244 | unsigned : 15; /**< Reserved. */ |
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| 245 | } __attribute__ ((packed)); |
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| 246 | }; |
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| 247 | typedef union lvt_error lvt_error_t; |
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| 248 | |||
| 514 | jermar | 249 | /** Local APIC ID Register. */ |
| 1 | jermar | 250 | #define L_APIC_ID (0x020/sizeof(__u32)) |
| 515 | jermar | 251 | union l_apic_id { |
| 514 | jermar | 252 | __u32 value; |
| 253 | struct { |
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| 254 | unsigned : 24; /**< Reserved. */ |
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| 255 | __u8 apic_id; /**< Local APIC ID. */ |
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| 256 | } __attribute__ ((packed)); |
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| 257 | }; |
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| 515 | jermar | 258 | typedef union l_apic_id l_apic_id_t; |
| 1 | jermar | 259 | |
| 1251 | jermar | 260 | /** Local APIC Version Register */ |
| 27 | jermar | 261 | #define LAVR (0x030/sizeof(__u32)) |
| 262 | #define LAVR_Mask 0xff |
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| 263 | #define is_local_apic(x) (((x)&LAVR_Mask&0xf0)==0x1) |
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| 264 | #define is_82489DX_apic(x) ((((x)&LAVR_Mask&0xf0)==0x0)) |
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| 265 | #define is_local_xapic(x) (((x)&LAVR_Mask)==0x14) |
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| 266 | |||
| 672 | jermar | 267 | /** Logical Destination Register. */ |
| 268 | #define LDR (0x0d0/sizeof(__u32)) |
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| 269 | union ldr { |
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| 270 | __u32 value; |
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| 271 | struct { |
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| 1251 | jermar | 272 | unsigned : 24; /**< Reserved. */ |
| 672 | jermar | 273 | __u8 id; /**< Logical APIC ID. */ |
| 274 | } __attribute__ ((packed)); |
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| 275 | }; |
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| 276 | typedef union ldr ldr_t; |
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| 277 | |||
| 278 | /** Destination Format Register. */ |
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| 279 | #define DFR (0x0e0/sizeof(__u32)) |
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| 280 | union dfr { |
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| 281 | __u32 value; |
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| 282 | struct { |
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| 283 | unsigned : 28; /**< Reserved, all ones. */ |
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| 284 | unsigned model : 4; /**< Model. */ |
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| 285 | } __attribute__ ((packed)); |
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| 286 | }; |
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| 287 | typedef union dfr dfr_t; |
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| 288 | |||
| 1 | jermar | 289 | /* IO APIC */ |
| 290 | #define IOREGSEL (0x00/sizeof(__u32)) |
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| 291 | #define IOWIN (0x10/sizeof(__u32)) |
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| 292 | |||
| 293 | #define IOAPICID 0x00 |
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| 294 | #define IOAPICVER 0x01 |
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| 295 | #define IOAPICARB 0x02 |
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| 296 | #define IOREDTBL 0x10 |
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| 297 | |||
| 514 | jermar | 298 | /** I/O Register Select Register. */ |
| 299 | union io_regsel { |
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| 300 | __u32 value; |
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| 301 | struct { |
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| 302 | __u8 reg_addr; /**< APIC Register Address. */ |
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| 303 | unsigned : 24; /**< Reserved. */ |
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| 304 | } __attribute__ ((packed)); |
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| 305 | }; |
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| 306 | typedef union io_regsel io_regsel_t; |
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| 307 | |||
| 512 | jermar | 308 | /** I/O Redirection Register. */ |
| 309 | struct io_redirection_reg { |
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| 310 | union { |
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| 311 | __u32 lo; |
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| 312 | struct { |
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| 513 | jermar | 313 | __u8 intvec; /**< Interrupt Vector. */ |
| 512 | jermar | 314 | unsigned delmod : 3; /**< Delivery Mode. */ |
| 315 | unsigned destmod : 1; /**< Destination mode. */ |
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| 316 | unsigned delivs : 1; /**< Delivery status (RO). */ |
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| 317 | unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ |
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| 318 | unsigned irr : 1; /**< Remote IRR (RO). */ |
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| 319 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
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| 320 | unsigned masked : 1; /**< Interrupt Mask. */ |
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| 321 | unsigned : 15; /**< Reserved. */ |
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| 513 | jermar | 322 | } __attribute__ ((packed)); |
| 512 | jermar | 323 | }; |
| 324 | union { |
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| 325 | __u32 hi; |
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| 326 | struct { |
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| 327 | unsigned : 24; /**< Reserved. */ |
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| 1251 | jermar | 328 | __u8 dest : 8; /**< Destination Field. */ |
| 513 | jermar | 329 | } __attribute__ ((packed)); |
| 512 | jermar | 330 | }; |
| 331 | |||
| 332 | } __attribute__ ((packed)); |
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| 333 | typedef struct io_redirection_reg io_redirection_reg_t; |
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| 334 | |||
| 515 | jermar | 335 | |
| 336 | /** IO APIC Identification Register. */ |
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| 337 | union io_apic_id { |
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| 338 | __u32 value; |
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| 339 | struct { |
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| 340 | unsigned : 24; /**< Reserved. */ |
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| 341 | unsigned apic_id : 4; /**< IO APIC ID. */ |
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| 342 | unsigned : 4; /**< Reserved. */ |
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| 343 | } __attribute__ ((packed)); |
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| 344 | }; |
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| 345 | typedef union io_apic_id io_apic_id_t; |
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| 346 | |||
| 1 | jermar | 347 | extern volatile __u32 *l_apic; |
| 348 | extern volatile __u32 *io_apic; |
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| 349 | |||
| 350 | extern __u32 apic_id_mask; |
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| 351 | |||
| 352 | extern void apic_init(void); |
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| 353 | |||
| 354 | extern void l_apic_init(void); |
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| 355 | extern void l_apic_eoi(void); |
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| 5 | jermar | 356 | extern int l_apic_broadcast_custom_ipi(__u8 vector); |
| 1 | jermar | 357 | extern int l_apic_send_init_ipi(__u8 apicid); |
| 358 | extern void l_apic_debug(void); |
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| 81 | jermar | 359 | extern __u8 l_apic_id(void); |
| 1 | jermar | 360 | |
| 361 | extern __u32 io_apic_read(__u8 address); |
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| 362 | extern void io_apic_write(__u8 address , __u32 x); |
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| 514 | jermar | 363 | extern void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags); |
| 1 | jermar | 364 | extern void io_apic_disable_irqs(__u16 irqmask); |
| 365 | extern void io_apic_enable_irqs(__u16 irqmask); |
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| 366 | |||
| 367 | #endif |
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| 1702 | cejka | 368 | |
| 369 | /** @} |
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| 370 | */ |
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| 371 |