Subversion Repositories HelenOS

/*

 * Copyright (c) 2008 Jiri Svoboda

 * All rights reserved.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions

 * are met:

 *

 * - Redistributions of source code must retain the above copyright

 *   notice, this list of conditions and the following disclaimer.

 * - Redistributions in binary form must reproduce the above copyright

 *   notice, this list of conditions and the following disclaimer in the

 *   documentation and/or other materials provided with the distribution.

 * - The name of the author may not be used to endorse or promote products

 *   derived from this software without specific prior written permission.

 *

 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR

 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.

 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,

 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT

 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,

 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY

 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF

 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */

/** @addtogroup debug

 * @{

 */

/** @file

 */

#include <stdio.h>

#include <stdlib.h>

#include <assert.h>

#include <sys/types.h>

#include <errno.h>

#include <udebug.h>

#include "../../../cons.h"

#include "../../../main.h"

#include "../../../breakpoint.h"

#include "../../../include/arch.h"

#include "../../../include/arch/arch.h"

#include "../../../genarch/idec/idec.h"

static istate_t istate;

typedef enum {

    /* Branch */

    OP_B,

    OP_BA,

    OP_BL,

    OP_BLA,

    /* Branch conditional */

    OP_BC,

    OP_BCA,

    OP_BCL,

    OP_BCLA,

    /* Branch conditional to counter register */

    OP_BCCTR,

    OP_BCCTRL,

    /* Branch conditional to link register */

    OP_BCLR,

    OP_BCLRL

} op_t;

typedef struct {

    uint32_t mask;

    uint32_t value;

    op_t op;

} instr_desc_t;

static instr_desc_t decoding_table[] = {

    { 0xfc000003, 0x48000000, OP_B },

    { 0xfc000003, 0x48000002, OP_BA },

    { 0xfc000003, 0x48000001, OP_BL },

    { 0xfc000003, 0x48000003, OP_BLA },

    { 0xfc000003, 0x40000000, OP_BC },

    { 0xfc000003, 0x40000002, OP_BCA },

    { 0xfc000003, 0x40000001, OP_BCL },

    { 0xfc000003, 0x40000003, OP_BCLA },

    { 0xfc00ffff, 0x4c000420, OP_BCCTR },

    { 0xfc00ffff, 0x4c000421, OP_BCCTRL },

    { 0xfc00ffff, 0x4c000020, OP_BCLR },

    { 0xfc00ffff, 0x4c000021, OP_BCLRL },

    { 0, 0, -1 }

};

/** Sign-extend a value to 32 bits.

 *

 * @param val   A signed value (of limited width)

 * @param bits  Bit-width of value.

 * @return The value extended to a 32-bit signed integer.

 */

#define EXTS(val, bits) ((int32_t)(val) << (32 - (bits)) >> (32 - (bits)))

/** (opcode mask) Branch instruction uses absolute address */

#define MASK_AA 0x00000002

/** (opcode mask) Branch instruction saves PC to the link register */

#define MASK_LK 0x00000001

void arch_dthread_initialize(dthread_t *dt)

{

    dt->arch.singlestep = false;

    bstore_initialize(&dt->arch.cur);

    bstore_initialize(&dt->arch.next[0]);

    bstore_initialize(&dt->arch.next[1]);

}

int arch_breakpoint_set(breakpoint_t *b)

{

    int rc;

    cons_printf("break=0x%x\n", OPCODE_BREAK);

    rc = idec_breakpoint_set(b);

    if (rc != 0) return rc;

    return 0;

}

int arch_breakpoint_remove(breakpoint_t *b)

{

    return idec_breakpoint_remove(b);

}

static int islot_read(uintptr_t addr, uint32_t *instr)

{

    int rc;

    rc = udebug_mem_read(app_phone, instr, addr, sizeof(uint32_t));

    if (rc != EOK) {

        cons_printf("Error reading memory address 0x%zx\n", addr);

    }

    return rc;

}

static op_t instr_decode(uint32_t instr)

{

    instr_desc_t *idesc;

    idesc = &decoding_table[0];

    while (idesc->op >= 0) {

        if ((instr & idesc->mask) == idesc->value)

            return idesc->op;

        ++idesc;

    }

    return -1;

}

static int get_ctr(dthread_t *dt, uint32_t *value)

{

    int rc;

    rc = udebug_regs_read(app_phone, dt->hash, &istate);

    if (rc < 0) return rc;

    *value = istate.ctr;

    printf("get_ctr ok (0x%08x)\n", *value);

    return 0;

}

static int get_lr(dthread_t *dt, uint32_t *value)

{

    int rc;

    rc = udebug_regs_read(app_phone, dt->hash, &istate);

    if (rc < 0) return rc;

    *value = istate.lr;

    printf("get_lr ok (0x%08x)\n", *value);

    return 0;

}

/** Get address of the instruction that will be executed after the current one.

 *

 * Assumptions: addr == PC, *addr is not covered by a BREAK.

 *

 * @param dt        Dthread on which to operate.

 * @param addr      Address of an instruction.

 * @param buffer    Buffer for storing up to 2 addresses.

 * @return      Number of stored addresses or negative error code.

 */

int get_next_addr(dthread_t *dt, uintptr_t addr, uintptr_t *buffer)

{

    uint32_t instr;

    int32_t li;

    int32_t bd;

    uint32_t ctr, lr;

    op_t op;

    int rc;

    int n;

    rc = islot_read(addr, &instr);

    if (rc != 0) return rc;

    op = instr_decode(instr);

    switch (op) {

    /* Branch (Bx) */

    case OP_B:

    case OP_BA:

    case OP_BL:

    case OP_BLA:

        /* LI is a 26-bit signed integer */

        li = EXTS(instr & 0x03fffffc, 26);

        if (instr & MASK_AA)

            buffer[0] = li;

        else

            buffer[0] = addr + li;

        n = 1;

        break;

    /* Branch conditional (BCx) */

    case OP_BC:

    case OP_BCA:

    case OP_BCL:

    case OP_BCLA:

        /* BD is a 16-bit signed integer */

        bd = EXTS(instr & 0x0000fffc, 16);

        if (instr & MASK_AA)

            buffer[0] = bd;

        else

            buffer[0] = addr + bd;

        buffer[1] = addr + 4;   /* not taken */

        n = 2;

        break;

    /* Branch conditional to counter register (BCCTRx) */

    case OP_BCCTR:

    case OP_BCCTRL:

        rc = get_ctr(dt, &ctr);

        if (rc != 0) return rc;

        buffer[0] = ctr & ~0x00000003;

        buffer[1] = addr + 4;   /* not taken */

        n = 2;

        break;

    /* Branch conditional to link register (BCLRx) */

    case OP_BCLR:

    case OP_BCLRL:

        rc = get_lr(dt, &lr);

        if (rc != 0) return rc;

        buffer[0] = lr & ~0x00000003;

        buffer[1] = addr + 4;   /* not taken */

        n = 2;

        break;

    default:

        /* Regular instruction */  

        buffer[0] = addr + 4;

        n = 1;

        break;

    }

    return n;

}

void arch_event_breakpoint(thash_t thread_hash)

{

    idec_event_breakpoint(thread_hash);

}

void arch_event_trap(dthread_t *dt)

{

    /* Unused */

    (void)dt;

}

void arch_dump_regs(thash_t thash)

{

    /* TODO */

}

void arch_singlestep(dthread_t *dt)

{

    idec_singlestep(dt);

}

/** @}

 */