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3862 rimsky 1 
/*
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 * Copyright (c) 2006 Jakub Jermar
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 * Copyright (c) 2009 Pavel Rimsky
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup sparc64mm  
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 * @{
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 */
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/** @file
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 */
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#include <arch/mm/tsb.h>
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#include <arch/mm/pagesize.h>
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#include <arch/mm/tlb.h>
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#include <arch/mm/page.h>
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#include <arch/barrier.h>
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#include <mm/as.h>
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#include <arch/types.h>
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#include <macros.h>
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#include <debug.h>
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#define TSB_INDEX_MASK  ((1 << (21 + 1 + TSB_SIZE - MMU_PAGE_WIDTH)) - 1)
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/** Invalidate portion of TSB.
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 *
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 * We assume that the address space is already locked. Note that respective
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 * portions of both TSBs are invalidated at a time.
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 *
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 * @param as    Address space.
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 * @param page  First page to invalidate in TSB.
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 * @param pages Number of pages to invalidate. Value of (count_t) -1 means the
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 *      whole TSB.
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 */
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void tsb_invalidate(as_t *as, uintptr_t page, count_t pages)
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{
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    index_t i0, i;
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    count_t cnt;
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    ASSERT(as->arch.tsb_description.tsb_base);
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    i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
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    ASSERT(i0 < TSB_ENTRY_COUNT);
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    if (pages == (count_t) - 1 || (pages) > TSB_ENTRY_COUNT)
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        cnt = TSB_ENTRY_COUNT;
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    else
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        cnt = pages;
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    for (i = 0; i < cnt; i++) {
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        ((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[
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            (i0 + i) & (TSB_ENTRY_COUNT - 1)].data.v = false;
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    }
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}
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/** Copy software PTE to ITSB.
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 *
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 * @param t     Software PTE.
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 */
4129 rimsky 83 
void itsb_pte_copy(pte_t *t)
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{
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    as_t *as;
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    tsb_entry_t *tsb;
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    index_t entry;
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    as = t->as;
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    entry = (t->page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
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    ASSERT(entry < TSB_ENTRY_COUNT);
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    tsb = &((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[entry];
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    /*
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     * We use write barriers to make sure that the TSB load
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     * won't use inconsistent data or that the fault will
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     * be repeated.
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     */
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    tsb->data.v = false;
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    write_barrier();
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    tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
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    tsb->data.value = 0;
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    tsb->data.nfo = false;
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    tsb->data.ra = t->frame >> MMU_FRAME_WIDTH;
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    tsb->data.ie = false;
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    tsb->data.e = false;
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    tsb->data.cp = t->c;    /* cp as cache in phys.-idxed, c as cacheable */
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    tsb->data.cv = false;
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    tsb->data.p = t->k; /* p as privileged, k as kernel */
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    tsb->data.x = true;
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    tsb->data.w = false;
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    tsb->data.size = PAGESIZE_8K;
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    write_barrier();
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    tsb->data.v = t->p; /* v as valid, p as present */
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}
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/** Copy software PTE to DTSB.
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 *
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 * @param t Software PTE.
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 * @param ro    If true, the mapping is copied read-only.
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 */
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void dtsb_pte_copy(pte_t *t, bool ro)
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{
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    as_t *as;
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    tsb_entry_t *tsb;
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    index_t entry;
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    as = t->as;
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    entry = (t->page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
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    ASSERT(entry < TSB_ENTRY_COUNT);
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    tsb = &((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[entry];
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    /*
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     * We use write barriers to make sure that the TSB load
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     * won't use inconsistent data or that the fault will
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     * be repeated.
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     */
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    tsb->data.v = false;
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    write_barrier();
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    tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
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    tsb->data.value = 0;
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    tsb->data.nfo = false;
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    tsb->data.ra = t->frame >> MMU_FRAME_WIDTH;
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    tsb->data.ie = false;
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    tsb->data.e = false;
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    tsb->data.cp = t->c;    /* cp as cache in phys.-idxed, c as cacheable */
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#ifdef CONFIG_VIRT_IDX_DCACHE
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    tsb->data.cv = t->c;
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#endif /* CONFIG_VIRT_IDX_DCACHE */
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    tsb->data.p = t->k; /* p as privileged, k as kernel */
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    tsb->data.x = true;
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    tsb->data.w = ro ? false : t->w;
4129 rimsky 163 
    tsb->data.size = PAGESIZE_8K;
3862 rimsky 164 
 
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    write_barrier();
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    tsb->data.v = t->p; /* v as valid, p as present */
3862 rimsky 168 
}
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/** @}
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 */
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