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Rev | Author | Line No. | Line |
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251 | palkovsky | 1 | /* |
2071 | jermar | 2 | * Copyright (c) 2001-2004 Jakub Jermar |
251 | palkovsky | 3 | * All rights reserved. |
4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
1731 | jermar | 29 | /** @addtogroup amd64 |
1702 | cejka | 30 | * @{ |
31 | */ |
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32 | /** @file |
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33 | */ |
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34 | |||
2089 | decky | 35 | #include <cpu.h> |
251 | palkovsky | 36 | #include <arch/cpu.h> |
37 | #include <arch/cpuid.h> |
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38 | #include <arch/pm.h> |
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39 | |||
40 | #include <arch.h> |
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41 | #include <arch/types.h> |
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42 | #include <print.h> |
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391 | jermar | 43 | #include <fpu_context.h> |
251 | palkovsky | 44 | |
45 | /* |
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46 | * Identification of CPUs. |
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47 | * Contains only non-MP-Specification specific SMP code. |
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48 | */ |
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49 | #define AMD_CPUID_EBX 0x68747541 |
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50 | #define AMD_CPUID_ECX 0x444d4163 |
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51 | #define AMD_CPUID_EDX 0x69746e65 |
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52 | |||
53 | #define INTEL_CPUID_EBX 0x756e6547 |
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54 | #define INTEL_CPUID_ECX 0x6c65746e |
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55 | #define INTEL_CPUID_EDX 0x49656e69 |
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56 | |||
57 | |||
58 | enum vendor { |
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2089 | decky | 59 | VendorUnknown = 0, |
251 | palkovsky | 60 | VendorAMD, |
61 | VendorIntel |
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62 | }; |
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63 | |||
64 | static char *vendor_str[] = { |
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65 | "Unknown Vendor", |
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66 | "AuthenticAMD", |
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67 | "GenuineIntel" |
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68 | }; |
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69 | |||
282 | palkovsky | 70 | |
71 | /** Setup flags on processor so that we can use the FPU |
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72 | * |
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73 | * cr0.osfxsr = 1 -> we do support fxstor/fxrestor |
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74 | * cr0.em = 0 -> we do not emulate coprocessor |
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75 | * cr0.mp = 1 -> we do want lazy context switch |
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76 | */ |
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77 | void cpu_setup_fpu(void) |
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78 | { |
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2082 | decky | 79 | asm volatile ( |
4017 | decky | 80 | "movq %%cr0, %%rax\n" |
81 | "btsq $1, %%rax\n" /* cr0.mp */ |
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82 | "btrq $2, %%rax\n" /* cr0.em */ |
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83 | "movq %%rax, %%cr0\n" |
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84 | |||
85 | "movq %%cr4, %%rax\n" |
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86 | "bts $9, %%rax\n" /* cr4.osfxsr */ |
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87 | "movq %%rax, %%cr4\n" |
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88 | ::: "%rax" |
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89 | ); |
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282 | palkovsky | 90 | } |
91 | |||
4017 | decky | 92 | /** Set the TS flag to 1. |
282 | palkovsky | 93 | * |
94 | * If a thread accesses coprocessor, exception is run, which |
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95 | * does a lazy fpu context switch. |
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96 | * |
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97 | */ |
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309 | palkovsky | 98 | void fpu_disable(void) |
251 | palkovsky | 99 | { |
4017 | decky | 100 | asm volatile ( |
101 | "mov %%cr0, %%rax\n" |
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102 | "bts $3, %%rax\n" |
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103 | "mov %%rax, %%cr0\n" |
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104 | ::: "%rax" |
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105 | ); |
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251 | palkovsky | 106 | } |
107 | |||
309 | palkovsky | 108 | void fpu_enable(void) |
251 | palkovsky | 109 | { |
4017 | decky | 110 | asm volatile ( |
111 | "mov %%cr0, %%rax\n" |
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112 | "btr $3, %%rax\n" |
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113 | "mov %%rax, %%cr0\n" |
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114 | ::: "%rax" |
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115 | ); |
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251 | palkovsky | 116 | } |
257 | palkovsky | 117 | |
118 | void cpu_arch_init(void) |
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119 | { |
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120 | CPU->arch.tss = tss_p; |
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2783 | jermar | 121 | CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - |
122 | ((uint8_t *) CPU->arch.tss); |
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1187 | jermar | 123 | CPU->fpu_owner = NULL; |
257 | palkovsky | 124 | } |
125 | |||
126 | void cpu_identify(void) |
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127 | { |
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128 | cpu_info_t info; |
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129 | |||
130 | CPU->arch.vendor = VendorUnknown; |
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131 | if (has_cpuid()) { |
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132 | cpuid(0, &info); |
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133 | |||
134 | /* |
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135 | * Check for AMD processor. |
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136 | */ |
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2783 | jermar | 137 | if (info.cpuid_ebx == AMD_CPUID_EBX && |
138 | info.cpuid_ecx == AMD_CPUID_ECX && |
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139 | info.cpuid_edx == AMD_CPUID_EDX) { |
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257 | palkovsky | 140 | CPU->arch.vendor = VendorAMD; |
141 | } |
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142 | |||
143 | /* |
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144 | * Check for Intel processor. |
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145 | */ |
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2783 | jermar | 146 | if (info.cpuid_ebx == INTEL_CPUID_EBX && |
147 | info.cpuid_ecx == INTEL_CPUID_ECX && |
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148 | info.cpuid_edx == INTEL_CPUID_EDX) { |
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257 | palkovsky | 149 | CPU->arch.vendor = VendorIntel; |
150 | } |
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151 | |||
152 | cpuid(1, &info); |
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2783 | jermar | 153 | CPU->arch.family = (info.cpuid_eax >> 8) & 0xf; |
154 | CPU->arch.model = (info.cpuid_eax >> 4) & 0xf; |
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155 | CPU->arch.stepping = (info.cpuid_eax >> 0) & 0xf; |
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257 | palkovsky | 156 | } |
157 | } |
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158 | |||
159 | void cpu_print_report(cpu_t* m) |
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160 | { |
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161 | printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n", |
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2783 | jermar | 162 | m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, |
163 | m->arch.stepping, m->frequency_mhz); |
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257 | palkovsky | 164 | } |
1702 | cejka | 165 | |
1731 | jermar | 166 | /** @} |
1702 | cejka | 167 | */ |