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2468 | jermar | 1 | /* |
2 | * Copyright (c) 2007 Pavel Jancik |
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3 | * Copyright (c) 2007 Michal Kebrt |
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4 | * All rights reserved. |
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5 | * |
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6 | * Redistribution and use in source and binary forms, with or without |
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7 | * modification, are permitted provided that the following conditions |
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8 | * are met: |
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9 | * |
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10 | * - Redistributions of source code must retain the above copyright |
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11 | * notice, this list of conditions and the following disclaimer. |
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12 | * - Redistributions in binary form must reproduce the above copyright |
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13 | * notice, this list of conditions and the following disclaimer in the |
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14 | * documentation and/or other materials provided with the distribution. |
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15 | * - The name of the author may not be used to endorse or promote products |
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16 | * derived from this software without specific prior written permission. |
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17 | * |
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18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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28 | */ |
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29 | |||
30 | |||
31 | /** @addtogroup arm32boot |
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32 | * @{ |
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33 | */ |
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34 | /** @file |
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35 | * @brief Memory management used while booting the kernel. |
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36 | * |
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37 | * So called "section" paging is used while booting the kernel. The term |
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38 | * "section" comes from the ARM architecture specification and stands for the |
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39 | * following: one-level paging, 1MB sized pages, 4096 entries in the page |
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40 | * table. |
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41 | */ |
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42 | |||
43 | |||
44 | #ifndef BOOT_arm32__MM_H |
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45 | #define BOOT_arm32__MM_H |
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46 | |||
47 | |||
48 | #ifndef __ASM__ |
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49 | #include "types.h" |
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50 | #endif |
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51 | |||
52 | |||
53 | /** Frame width. */ |
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54 | #define FRAME_WIDTH 20 |
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55 | |||
56 | /** Frame size. */ |
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57 | #define FRAME_SIZE (1 << FRAME_WIDTH) |
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58 | |||
59 | /** Page size in 2-level paging which is switched on later after the kernel |
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60 | * initialization. |
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61 | */ |
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62 | #define KERNEL_PAGE_SIZE (1 << 12) |
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63 | |||
64 | |||
65 | #ifndef __ASM__ |
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66 | /** Converts kernel address to physical address. */ |
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67 | # define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) |
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68 | /** Converts physical address to kernel address. */ |
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69 | # define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) |
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70 | #else |
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71 | # define KA2PA(x) ((x) - 0x80000000) |
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72 | # define PA2KA(x) ((x) + 0x80000000) |
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73 | #endif |
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74 | |||
75 | |||
76 | /** Number of entries in PTL0. */ |
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77 | #define PTL0_ENTRIES (1 << 12) /* 4096 */ |
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78 | |||
79 | /** Size of an entry in PTL0. */ |
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80 | #define PTL0_ENTRY_SIZE 4 |
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81 | |||
82 | /** Returns number of frame the address belongs to. */ |
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83 | #define ADDR2PFN(addr) (((uintptr_t) (addr)) >> FRAME_WIDTH) |
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84 | |||
85 | /** Describes "section" page table entry (one-level paging with 1MB sized pages). */ |
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86 | #define PTE_DESCRIPTOR_SECTION 0x2 |
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87 | |||
88 | /** Page table access rights: user - no access, kernel - read/write. */ |
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89 | #define PTE_AP_USER_NO_KERNEL_RW 0x1 |
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90 | |||
91 | |||
92 | #ifndef __ASM__ |
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93 | |||
94 | |||
95 | /** Page table level 0 entry - "section" format is used (one-level paging, 1MB |
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96 | * sized pages). Used only while booting the kernel. |
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97 | */ |
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98 | typedef struct { |
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99 | unsigned descriptor_type : 2; |
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100 | unsigned bufferable : 1; |
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101 | unsigned cacheable : 1; |
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102 | unsigned impl_specific : 1; |
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103 | unsigned domain : 4; |
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104 | unsigned should_be_zero_1 : 1; |
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105 | unsigned access_permission : 2; |
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106 | unsigned should_be_zero_2 : 8; |
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107 | unsigned section_base_addr : 12; |
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108 | } __attribute__ ((packed)) pte_level0_section_t; |
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109 | |||
110 | |||
111 | /** Page table that holds 1:1 virtual to physical mapping used while booting the |
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112 | * kernel. |
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113 | */ |
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114 | extern pte_level0_section_t page_table[PTL0_ENTRIES]; |
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115 | |||
116 | extern void mmu_start(void); |
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117 | |||
118 | |||
119 | /** Enables paging. */ |
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120 | static inline void enable_paging() |
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121 | { |
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122 | /* c3 - each two bits controls access to the one of domains (16) |
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123 | * 0b01 - behave as a client (user) of a domain |
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124 | */ |
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125 | asm volatile ( |
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126 | /* behave as a client of domains */ |
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127 | "ldr r0, =0x55555555\n" |
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128 | "mcr p15, 0, r0, c3, c0, 0\n" |
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129 | |||
130 | /* current settings */ |
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131 | "mrc p15, 0, r0, c1, c0, 0\n" |
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132 | |||
133 | /* mask to enable paging */ |
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134 | "ldr r1, =0x00000001\n" |
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135 | "orr r0, r0, r1\n" |
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136 | |||
137 | /* store settings */ |
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138 | "mcr p15, 0, r0, c1, c0, 0\n" |
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139 | : |
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140 | : |
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141 | : "r0", "r1" |
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142 | ); |
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143 | } |
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144 | |||
145 | |||
146 | /** Sets the address of level 0 page table to CP15 register 2. |
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147 | * |
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148 | * @param pt Address of a page table to set. |
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149 | */ |
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150 | static inline void set_ptl0_address(pte_level0_section_t* pt) |
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151 | { |
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152 | asm volatile ( |
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153 | "mcr p15, 0, %0, c2, c0, 0\n" |
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154 | : |
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155 | : "r" (pt) |
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156 | ); |
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157 | } |
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158 | |||
159 | |||
160 | #endif |
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161 | |||
162 | #endif |
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163 | |||
164 | /** @} |
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165 | */ |
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166 |