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Rev | Author | Line No. | Line |
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982 | decky | 1 | /* |
2071 | jermar | 2 | * Copyright (c) 2006 Martin Decky |
4718 | mejdrech | 3 | * Copyright (c) 2009 Jiri Svoboda |
982 | decky | 4 | * All rights reserved. |
5 | * |
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6 | * Redistribution and use in source and binary forms, with or without |
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7 | * modification, are permitted provided that the following conditions |
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8 | * are met: |
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9 | * |
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10 | * - Redistributions of source code must retain the above copyright |
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11 | * notice, this list of conditions and the following disclaimer. |
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12 | * - Redistributions in binary form must reproduce the above copyright |
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13 | * notice, this list of conditions and the following disclaimer in the |
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14 | * documentation and/or other materials provided with the distribution. |
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15 | * - The name of the author may not be used to endorse or promote products |
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16 | * derived from this software without specific prior written permission. |
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17 | * |
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18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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28 | */ |
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29 | |||
4311 | decky | 30 | /** @addtogroup genarch |
1702 | cejka | 31 | * @{ |
32 | */ |
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33 | /** @file |
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34 | */ |
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35 | |||
4311 | decky | 36 | #include <genarch/drivers/via-cuda/cuda.h> |
37 | #include <console/chardev.h> |
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38 | #include <ddi/irq.h> |
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982 | decky | 39 | #include <arch/asm.h> |
4311 | decky | 40 | #include <mm/slab.h> |
4148 | decky | 41 | #include <ddi/device.h> |
4718 | mejdrech | 42 | #include <synch/spinlock.h> |
982 | decky | 43 | |
4718 | mejdrech | 44 | static irq_ownership_t cuda_claim(irq_t *irq); |
45 | static void cuda_irq_handler(irq_t *irq); |
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1619 | decky | 46 | |
4718 | mejdrech | 47 | static void cuda_irq_listen(irq_t *irq); |
48 | static void cuda_irq_receive(irq_t *irq); |
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49 | static void cuda_irq_rcv_end(irq_t *irq, void *buf, size_t *len); |
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50 | static void cuda_irq_send_start(irq_t *irq); |
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51 | static void cuda_irq_send(irq_t *irq); |
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982 | decky | 52 | |
4718 | mejdrech | 53 | static void cuda_packet_handle(cuda_instance_t *instance, uint8_t *buf, size_t len); |
54 | static void cuda_send_start(cuda_instance_t *instance); |
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55 | static void cuda_autopoll_set(cuda_instance_t *instance, bool enable); |
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56 | |||
57 | /** B register fields */ |
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58 | enum { |
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59 | TREQ = 0x08, |
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60 | TACK = 0x10, |
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61 | TIP = 0x20 |
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62 | }; |
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63 | |||
64 | /** IER register fields */ |
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65 | enum { |
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66 | IER_CLR = 0x00, |
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67 | IER_SET = 0x80, |
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68 | |||
69 | SR_INT = 0x04, |
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70 | ALL_INT = 0x7f |
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71 | }; |
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72 | |||
73 | /** ACR register fields */ |
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74 | enum { |
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75 | SR_OUT = 0x10 |
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76 | }; |
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77 | |||
78 | /** Packet types */ |
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79 | enum { |
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80 | PT_ADB = 0x00, |
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81 | PT_CUDA = 0x01 |
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82 | }; |
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83 | |||
84 | /** CUDA packet types */ |
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85 | enum { |
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86 | CPT_AUTOPOLL = 0x01 |
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87 | }; |
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88 | |||
4311 | decky | 89 | cuda_instance_t *cuda_init(cuda_t *dev, inr_t inr, cir_t cir, void *cir_arg) |
1628 | decky | 90 | { |
4311 | decky | 91 | cuda_instance_t *instance |
92 | = malloc(sizeof(cuda_instance_t), FRAME_ATOMIC); |
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93 | if (instance) { |
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94 | instance->cuda = dev; |
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95 | instance->kbrdin = NULL; |
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4718 | mejdrech | 96 | instance->xstate = cx_listen; |
97 | instance->bidx = 0; |
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98 | instance->snd_bytes = 0; |
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99 | |||
100 | spinlock_initialize(&instance->dev_lock, "cuda_dev"); |
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101 | |||
102 | /* Disable all interrupts from CUDA. */ |
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103 | pio_write_8(&dev->ier, IER_CLR | ALL_INT); |
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104 | |||
4311 | decky | 105 | irq_initialize(&instance->irq); |
106 | instance->irq.devno = device_assign_devno(); |
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107 | instance->irq.inr = inr; |
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108 | instance->irq.claim = cuda_claim; |
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109 | instance->irq.handler = cuda_irq_handler; |
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110 | instance->irq.instance = instance; |
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111 | instance->irq.cir = cir; |
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112 | instance->irq.cir_arg = cir_arg; |
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4718 | mejdrech | 113 | instance->irq.preack = true; |
1633 | decky | 114 | } |
1619 | decky | 115 | |
4311 | decky | 116 | return instance; |
990 | decky | 117 | } |
118 | |||
4718 | mejdrech | 119 | #include <print.h> |
4311 | decky | 120 | void cuda_wire(cuda_instance_t *instance, indev_t *kbrdin) |
1628 | decky | 121 | { |
4718 | mejdrech | 122 | cuda_t *dev = instance->cuda; |
123 | |||
124 | ASSERT(instance); |
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125 | ASSERT(kbrdin); |
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126 | |||
127 | instance->kbrdin = kbrdin; |
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128 | irq_register(&instance->irq); |
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129 | |||
130 | /* Enable SR interrupt. */ |
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131 | pio_write_8(&dev->ier, TIP | TREQ); |
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132 | pio_write_8(&dev->ier, IER_SET | SR_INT); |
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133 | |||
134 | /* Enable ADB autopolling. */ |
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135 | cuda_autopoll_set(instance, true); |
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1628 | decky | 136 | } |
137 | |||
4718 | mejdrech | 138 | static irq_ownership_t cuda_claim(irq_t *irq) |
139 | { |
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140 | cuda_instance_t *instance = irq->instance; |
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141 | cuda_t *dev = instance->cuda; |
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142 | uint8_t ifr; |
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1702 | cejka | 143 | |
4718 | mejdrech | 144 | spinlock_lock(&instance->dev_lock); |
145 | ifr = pio_read_8(&dev->ifr); |
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146 | spinlock_unlock(&instance->dev_lock); |
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147 | |||
148 | if ((ifr & SR_INT) == 0) |
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149 | return IRQ_DECLINE; |
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150 | |||
151 | return IRQ_ACCEPT; |
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152 | } |
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153 | |||
154 | static void cuda_irq_handler(irq_t *irq) |
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155 | { |
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156 | cuda_instance_t *instance = irq->instance; |
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157 | uint8_t rbuf[CUDA_RCV_BUF_SIZE]; |
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158 | size_t len; |
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159 | bool handle; |
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160 | |||
161 | handle = false; |
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162 | len = 0; |
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163 | |||
164 | spinlock_lock(&instance->dev_lock); |
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165 | |||
166 | /* Lower IFR.SR_INT so that CUDA can generate next int by raising it. */ |
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167 | pio_write_8(&instance->cuda->ifr, SR_INT); |
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168 | |||
169 | switch (instance->xstate) { |
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170 | case cx_listen: cuda_irq_listen(irq); break; |
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171 | case cx_receive: cuda_irq_receive(irq); break; |
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172 | case cx_rcv_end: cuda_irq_rcv_end(irq, rbuf, &len); |
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173 | handle = true; break; |
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174 | case cx_send_start: cuda_irq_send_start(irq); break; |
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175 | case cx_send: cuda_irq_send(irq); break; |
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176 | } |
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177 | |||
178 | spinlock_unlock(&instance->dev_lock); |
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179 | |||
180 | /* Handle an incoming packet. */ |
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181 | if (handle) |
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182 | cuda_packet_handle(instance, rbuf, len); |
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183 | } |
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184 | |||
185 | /** Interrupt in listen state. |
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186 | * |
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187 | * Start packet reception. |
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188 | */ |
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189 | static void cuda_irq_listen(irq_t *irq) |
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190 | { |
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191 | cuda_instance_t *instance = irq->instance; |
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192 | cuda_t *dev = instance->cuda; |
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193 | uint8_t b; |
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194 | |||
195 | b = pio_read_8(&dev->b); |
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196 | |||
197 | if ((b & TREQ) != 0) { |
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198 | printf("cuda_irq_listen: no TREQ?!\n"); |
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199 | return; |
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200 | } |
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201 | |||
202 | pio_read_8(&dev->sr); |
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203 | pio_write_8(&dev->b, pio_read_8(&dev->b) & ~TIP); |
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204 | instance->xstate = cx_receive; |
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205 | } |
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206 | |||
207 | /** Interrupt in receive state. |
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208 | * |
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209 | * Receive next byte of packet. |
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210 | */ |
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211 | static void cuda_irq_receive(irq_t *irq) |
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212 | { |
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213 | cuda_instance_t *instance = irq->instance; |
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214 | cuda_t *dev = instance->cuda; |
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215 | uint8_t b, data; |
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216 | |||
217 | data = pio_read_8(&dev->sr); |
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218 | if (instance->bidx < CUDA_RCV_BUF_SIZE) |
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219 | instance->rcv_buf[instance->bidx++] = data; |
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220 | |||
221 | b = pio_read_8(&dev->b); |
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222 | |||
223 | if ((b & TREQ) == 0) { |
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224 | pio_write_8(&dev->b, b ^ TACK); |
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225 | } else { |
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226 | pio_write_8(&dev->b, b | TACK | TIP); |
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227 | instance->xstate = cx_rcv_end; |
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228 | } |
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229 | } |
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230 | |||
231 | /** Interrupt in rcv_end state. |
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232 | * |
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233 | * Terminate packet reception. Either go back to listen state or start |
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234 | * receiving another packet if CUDA has one for us. |
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235 | */ |
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236 | static void cuda_irq_rcv_end(irq_t *irq, void *buf, size_t *len) |
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237 | { |
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238 | cuda_instance_t *instance = irq->instance; |
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239 | cuda_t *dev = instance->cuda; |
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240 | uint8_t data, b; |
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241 | |||
242 | b = pio_read_8(&dev->b); |
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243 | data = pio_read_8(&dev->sr); |
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244 | |||
245 | if ((b & TREQ) == 0) { |
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246 | instance->xstate = cx_receive; |
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247 | pio_write_8(&dev->b, b & ~TIP); |
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248 | } else { |
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249 | instance->xstate = cx_listen; |
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250 | cuda_send_start(instance); |
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251 | } |
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252 | |||
253 | memcpy(buf, instance->rcv_buf, instance->bidx); |
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254 | *len = instance->bidx; |
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255 | instance->bidx = 0; |
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256 | } |
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257 | |||
258 | /** Interrupt in send_start state. |
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259 | * |
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260 | * Process result of sending first byte (and send second on success). |
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261 | */ |
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262 | static void cuda_irq_send_start(irq_t *irq) |
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263 | { |
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264 | cuda_instance_t *instance = irq->instance; |
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265 | cuda_t *dev = instance->cuda; |
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266 | uint8_t b; |
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267 | |||
268 | b = pio_read_8(&dev->b); |
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269 | |||
270 | if ((b & TREQ) == 0) { |
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271 | /* Collision */ |
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272 | pio_write_8(&dev->acr, pio_read_8(&dev->acr) & ~SR_OUT); |
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273 | pio_read_8(&dev->sr); |
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274 | pio_write_8(&dev->b, pio_read_8(&dev->b) | TIP | TACK); |
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275 | instance->xstate = cx_listen; |
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276 | return; |
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277 | } |
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278 | |||
279 | pio_write_8(&dev->sr, instance->snd_buf[1]); |
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280 | pio_write_8(&dev->b, pio_read_8(&dev->b) ^ TACK); |
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281 | instance->bidx = 2; |
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282 | |||
283 | instance->xstate = cx_send; |
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284 | } |
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285 | |||
286 | /** Interrupt in send state. |
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287 | * |
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288 | * Send next byte or terminate transmission. |
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289 | */ |
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290 | static void cuda_irq_send(irq_t *irq) |
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291 | { |
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292 | cuda_instance_t *instance = irq->instance; |
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293 | cuda_t *dev = instance->cuda; |
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294 | |||
295 | if (instance->bidx < instance->snd_bytes) { |
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296 | /* Send next byte. */ |
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297 | pio_write_8(&dev->sr, instance->snd_buf[instance->bidx++]); |
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298 | pio_write_8(&dev->b, pio_read_8(&dev->b) ^ TACK); |
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299 | return; |
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300 | } |
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301 | |||
302 | /* End transfer. */ |
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303 | instance->snd_bytes = 0; |
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304 | instance->bidx = 0; |
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305 | |||
306 | pio_write_8(&dev->acr, pio_read_8(&dev->acr) & ~SR_OUT); |
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307 | pio_read_8(&dev->sr); |
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308 | pio_write_8(&dev->b, pio_read_8(&dev->b) | TACK | TIP); |
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309 | |||
310 | instance->xstate = cx_listen; |
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311 | /* TODO: Match reply with request. */ |
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312 | } |
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313 | |||
314 | static void cuda_packet_handle(cuda_instance_t *instance, uint8_t *data, size_t len) |
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315 | { |
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316 | if (data[0] != 0x00 || data[1] != 0x40 || (data[2] != 0x2c |
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317 | && data[2] != 0x8c)) |
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318 | return; |
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319 | |||
320 | /* The packet contains one or two scancodes. */ |
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321 | if (data[3] != 0xff) |
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322 | indev_push_character(instance->kbrdin, data[3]); |
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323 | if (data[4] != 0xff) |
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324 | indev_push_character(instance->kbrdin, data[4]); |
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325 | } |
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326 | |||
327 | static void cuda_autopoll_set(cuda_instance_t *instance, bool enable) |
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328 | { |
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329 | instance->snd_buf[0] = PT_CUDA; |
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330 | instance->snd_buf[1] = CPT_AUTOPOLL; |
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331 | instance->snd_buf[2] = enable ? 0x01 : 0x00; |
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332 | instance->snd_bytes = 3; |
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333 | instance->bidx = 0; |
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334 | |||
335 | cuda_send_start(instance); |
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336 | } |
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337 | |||
338 | static void cuda_send_start(cuda_instance_t *instance) |
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339 | { |
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340 | cuda_t *dev = instance->cuda; |
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341 | |||
342 | ASSERT(instance->xstate == cx_listen); |
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343 | |||
344 | if (instance->snd_bytes == 0) |
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345 | return; |
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346 | |||
347 | /* Check for incoming data. */ |
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348 | if ((pio_read_8(&dev->b) & TREQ) == 0) |
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349 | return; |
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350 | |||
351 | pio_write_8(&dev->acr, pio_read_8(&dev->acr) | SR_OUT); |
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352 | pio_write_8(&dev->sr, instance->snd_buf[0]); |
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353 | pio_write_8(&dev->b, pio_read_8(&dev->b) & ~TIP); |
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354 | |||
355 | instance->xstate = cx_send_start; |
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356 | } |
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357 | |||
358 | |||
1734 | decky | 359 | /** @} |
1702 | cejka | 360 | */ |