| Rev |
Age |
Author |
Path |
Log message |
Diff |
| 860 |
6657 d 16 h |
decky |
/kernel/trunk/ |
indentation changes
ppc32 fpu context save/restore
ppc32 CPU version
ppc32 memcpy |
|
| 822 |
6669 d 17 h |
palkovsky |
/kernel/trunk/ |
Changed malloc to include second parameter and documented
recommended usage.
Added zone merging, made ia32 & amd64 to merge found zones. |
|
| 820 |
6669 d 18 h |
jermar |
/kernel/trunk/ |
Convert size_t, count_t and index_t to 64-bits on 64-bit architectures.
Change some pfn_t usages to count_t, size_t and index_t. |
|
| 817 |
6670 d 2 h |
palkovsky |
/kernel/trunk/ |
Small cleanup. |
|
| 814 |
6670 d 4 h |
palkovsky |
/kernel/trunk/ |
Cleanup o frame allocator.
Removed early_malloc & initial heap.
Will break ia64, ppc & sparc.
Added e820 table print. |
|
| 799 |
6671 d 19 h |
palkovsky |
/kernel/trunk/ |
Preliminary work on AMD userspace. |
|
| 794 |
6672 d 0 h |
palkovsky |
/kernel/trunk/ |
Added MIPS userspace. Currently can't make it work in gxemul. |
|
| 789 |
6672 d 18 h |
palkovsky |
/kernel/trunk/generic/ |
Early SLAB initialization, the cpu-cache is initialized later.
If you want to use slab_cache_create befor slab_cpu_enable, add
a flag SLAB_CACHE_MAGDEFERRED. |
|
| 773 |
6674 d 14 h |
palkovsky |
/kernel/trunk/ |
Added slab stress test.
Fixed race condition in slab allocator.
Moved initialization of slab to the point where we know correct config.cpu_count
Correctly passes tests on amd64, ia32 in both bochs & qemu. |
|
| 759 |
6676 d 14 h |
palkovsky |
/kernel/trunk/ |
Skeleton of SLAB allocator. |
|
| 757 |
6676 d 19 h |
jermar |
/kernel/trunk/ |
Blacklist addresses between 0xa0000 and 0xfffff on ia64 for frame allocator.
This area contains VGA text frame buffer and should be avoided.
falloc2 test now passes on ia64. |
|
| 756 |
6677 d 16 h |
jermar |
/kernel/trunk/ |
Memory management work.
Remove the last (i.e. 'root') argument from page_mapping_insert() and page_mapping_find().
Page table address is now extracted from the first (i.e. 'as') argument.
Add a lot of infrastructure to make the above possible.
sparc64 is now broken, most likely because of insufficient identity mapping of physical memory. |
|
| 755 |
6678 d 15 h |
jermar |
/kernel/trunk/ |
Change page_mapping_find/insert interfaces to take as_t * as first argument
and not asid_t as second argument. This change was necessitated by the
removal of mapping array from as_area_t and the fact that an address
space doesn't have an ASID when it is created. |
|
| 754 |
6678 d 16 h |
jermar |
/kernel/trunk/generic/ |
Remove address space area mapping array.
The information is to be stored directly in page tables.
This is to better support 64-bit systems which can have
fairly large address space areas. |
|
| 727 |
6689 d 18 h |
jermar |
/kernel/trunk/ |
New ASID management subsystem (initial work, more is required).
Some TLB invalidation changes. |
|
| 724 |
6691 d 19 h |
palkovsky |
/kernel/trunk/ |
Commit of the falloc_bad branch to trunk (719:723). |
|
| 718 |
6693 d 19 h |
decky |
/kernel/trunk/ |
interface change: as_area_load_mapping -> as_area_set_mapping (set single page mapping)
map init directly from the physical frames it is loaded in |
|
| 717 |
6693 d 21 h |
decky |
/kernel/trunk/ |
remove obsolete in-kernel userspace code
remove CONFIG_USERSPACE switch, uspace support is configured at run-time |
|
| 703 |
6696 d 3 h |
jermar |
/kernel/trunk/ |
Memory management work.
- vm.* -> as.* (as like address space is, imho, more fitting)
- Don't do TLB shootdown on vm_install(). Some architectures only need to call tlb_invalidate_asid().
- Don't allocate all frames for as_area in as_area_create(), but let them be allocated on-demand by as_page_fault().
- Add high-level page fault handler as_page_fault().
- Add as_area_load_mapping(). |
|
| 684 |
6701 d 1 h |
jermar |
/kernel/trunk/ |
Memory management work.
Move generic 4-level page table interface to genarch
and enable architectures to use different virtual memory
mechanisms (e.g. page hash tables).
Start page hash table support.
Switch ia64 and sparc64 to page hash tables.
Other architectures keep on using 4-level page table interface. |
|