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(root)/trunk/kernel/arch/sparc64/include/mm/mmu.h – Rev 1823

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Rev	Age	Author	Path	Log message	Diff
1823	6481 d 0 h	jermar	/trunk/kernel/arch/sparc64/	sparc64 work. Dump take_over_tlb_and_tt() and add its assembly language replacement.
1822	6481 d 5 h	jermar	/trunk/	sparc64 work. 1. Formatting fixes. 2. When writing to DMMU ASI's, simple membar() can be used in place of flush(). 3. Substantial changes in the way the TLB is taken over. 4. Remove unneeded functions. This is the first revision that also runs on a real world Ultra 5 with UltraSPARC IIi processor. Note that 3. needs further work as the current implementation depends on the fact that the compiler will use registers for local variables in take_over_tlb_and_tt(). Rewrite of that function into assembly is to follow.
1787	6501 d 21 h	decky	/	move kernel/trunk, uspace/trunk and boot/trunk to trunk/kernel, trunk/uspace and trunk/boot
1780	6508 d 23 h	jermar	/kernel/trunk/	Replace old __u?? types with respective C99 variants (e.g. uint32_t, int64_t, uintptr_t etc.).
1702	6530 d 1 h	cejka	/kernel/trunk/	Kernel doxygen comments updated.
758	6661 d 17 h	jermar	/kernel/trunk/arch/	sparc64 bugfix. When disabling IMMU and DMMU the kernel has to perform synchronization operation (e.g flush %r or membar #Sync instruction). There is no guarantee that the address contained in %r is in DTLB and therefore the flush instruction can fault. Normally this would be recognized and fixed by the OpenFirmware Fast Data MMU fault handler. However, this handler lives in virtually mapped memory and an attempt to execute there while the MMUs are disabled would result in a nested trap leading to error state. Replacing flush %r instruction with membar #Sync, wich is sufficient in this case, fixes this problem.
658	6703 d 5 h	jermar	/kernel/trunk/arch/sparc64/include/	sparc64 work. Add functions to read and write TICK and TICK_compare registers. Add types describing TICK and TICK_compare registers.
619	6711 d 14 h	jermar	/kernel/trunk/arch/sparc64/	sparc64 work. Functions for disabling/enabling MMU. TLB initialization. Identity mapping of first 4M for kernel. Switch to kernel copy of trap table.