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(root)/tags/0.1.1/kernel/genarch/include/mm/page_pt.h – Rev 1968

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Rev	Age	Author	Path	Log message	Diff
1968	6414 d 7 h	jermar	/tags/	Canonize pre-0.2.0.3 tags: remove inner branches, tags and trunk directories. The change now should reflect how those releases looked like after checkout.
1963	6414 d 8 h	jermar	/tags/0.1.1/	Tagging release 0.1.1
1108	6633 d 7 h	jermar	/kernel/trunk/	Small PTE_* macros and SET_PTL0_ADDRESS macro changes.
977	6641 d 15 h	jermar	/kernel/trunk/	Add sys_mremap() syscall.
832	6673 d 7 h	jermar	/kernel/trunk/	Change pt_mapping_remove() to deallocate frames for empty PTL1, PTL2 and PTL3.
793	6677 d 14 h	jermar	/kernel/trunk/	Use hash_table_get_instance instead of list_get_instance. Rename page_operations to page_mapping_operations. Rename page_pt_operations to pt_mapping_operations. Rename page_ht_operations to ht_mapping_operations.
760	6681 d 17 h	jermar	/kernel/trunk/	mips32 is not supposed to allocate page table. This is done by the generic code now. Remove PTL0 pointer as it is not needed. Remove GET_PTL0_ADDRESS from kernel. Update sparc64 comments in barrier.h.
756	6683 d 5 h	jermar	/kernel/trunk/	Memory management work. Remove the last (i.e. 'root') argument from page_mapping_insert() and page_mapping_find(). Page table address is now extracted from the first (i.e. 'as') argument. Add a lot of infrastructure to make the above possible. sparc64 is now broken, most likely because of insufficient identity mapping of physical memory.
755	6684 d 5 h	jermar	/kernel/trunk/	Change page_mapping_find/insert interfaces to take as_t * as first argument and not asid_t as second argument. This change was necessitated by the removal of mapping array from as_area_t and the fact that an address space doesn't have an ASID when it is created.
684	6706 d 14 h	jermar	/kernel/trunk/	Memory management work. Move generic 4-level page table interface to genarch and enable architectures to use different virtual memory mechanisms (e.g. page hash tables). Start page hash table support. Switch ia64 and sparc64 to page hash tables. Other architectures keep on using 4-level page table interface.