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Rev Age Author Path Log message Diff
3770 5609 d 10 h rimsky /branches/sparc/ Working on Niagara port - TLB initialization, MMU fault status area initialization, hypercall enhancement, modified tick.c so that the (hyperprivileged) TICK register does not have to be accessed. Now the initialization phase proceeds, but some parts of it are omitted for now (e.g. CPU initialization).  
3743 5616 d 18 h rimsky /branches/sparc/ Started to implement support for sun4v. Bootloader adapted to autodetect the architecture (sun4u, sun4v). Some generic sparc64 kernel files split into sun4u and sun4v versions (but the sun4u is still the default in many cases - in order to keep the code compilable). Implemented taking over the MMU. Implemented routines for performing the hypervisor API calls. Implemented a trivial standard output driver. HelenOS banner can now be printed from the kernel on Niagara.  
3742 5616 d 19 h rimsky /branches/sparc/ The sparc branch synchronized with trunk at revision 3722 (trunk@3722).  
3618 5650 d 9 h rimsky /branches/sparc/ Support for framebuffers, where the first pixel is mapped to a different address than the OBP 'reg' property claims. Cleanup, comments, C-style.  
3591 5655 d 17 h rimsky /branches/sparc/ Making the code compatible also with US-IV (US-IV+) - TLB size based on CPU autodetection, cleanup of code waking up APs. General cleanup.  
3493 5686 d 10 h rimsky /branches/sparc/ More changes making the code US-III-conformant (mainly in mm).  
3489 5693 d 12 h rimsky /branches/sparc/ More files made conform the US-III specification. (Changes concern mainly TSB.)  
3450 5715 d 10 h rimsky /branches/sparc/kernel/arch/sparc64/ Made tlb.h conform US-III specification.  
3440 5716 d 19 h rimsky /branches/sparc/kernel/arch/sparc64/ TLB modifications in order to make functions tlb_print and tlb_invalidate_all work correctly in US-III.  
3343 5745 d 14 h decky /branches/sparc/ add sparc branch  
3133 5812 d 11 h jermar /trunk/kernel/arch/ Add smc_coherence() macro to all architectures.
So far, only amd64, ia32, ia64 and sparc64 are implemented.
 
3104 5820 d 0 h svoboda /trunk/kernel/ Declare arguments for memstr.h operations as pointers instead of uintptr_t.  
2745 5919 d 19 h decky /trunk/ code cleanup (mostly signed/unsigned)
allow extra compiler warnings
 
2725 5940 d 17 h decky /trunk/kernel/ remove config.memory_size, get_memory_size() and memory_init.{c|d}
the amount of available memory can be calculated from the sizes of the zones
add FRAMES2SIZE, SIZE2KB and SIZE2MB functions/macros (code readability)
 
2462 6185 d 11 h jermar /trunk/kernel/ Replace gcc-specific __FUNCTION__ with C99 __func__.
suncc's xregs=no%float can be used only on sparc64.
 
2272 6233 d 13 h jermar /trunk/kernel/ Indentation and formatting fixes.  
2267 6235 d 12 h jermar /trunk/kernel/arch/sparc64/src/mm/ Fix indentation.  
2266 6235 d 12 h jermar /trunk/kernel/arch/sparc64/src/mm/ Add few assertions to tsb.c and clean it up a little bit.  
2252 6237 d 10 h jermar /trunk/kernel/arch/sparc64/src/mm/ Move one MEMBAR instruction from a delay slot,
which is, due to SF Erratum #51, a potentionally
dangerous place for a MEMBAR to be.
 
2231 6243 d 15 h jermar /trunk/kernel/arch/sparc64/ Fix a nasty bug in the TLB miss handlers on sparc64.
After we no longer lock the kernel stack in the DTLB,
there is a real danger of nested DTLB misses. The nested
miss can very easily clobber the DTLB Tag Access register.
Therefore, the original miss may not read this register, but
it has to receive its value as an argument. The argument
value is saved in the trap table when it is guaranteed that
the nested TLB miss will not occur.
 

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