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Rev Age Author Path Log message Diff
4383 5474 d 21 h rimsky /branches/sparc/kernel/arch/sparc64/ Fixed instruction access exception and data access exception in the trap table. Added new traps defined by UltraSPARC Architecture 2007 (which UltraSPARC T2 follows).  
4369 5478 d 15 h rimsky /branches/sparc/kernel/arch/sparc64/ Kernel stack and userspace window buffer pointers are stored in scratchpad registers instead of memory.  
4130 5534 d 15 h rimsky /branches/sparc/ Cleanup of the Niagara port. The main purpose of these changes is to make it easy to find out which code is generic, which is sun4u-specific and which is sun4v-specific.  
4129 5535 d 11 h rimsky /branches/sparc/kernel/arch/sparc64/ Implemented missing features in Niagara memory management, minor cleanup.  
4073 5537 d 14 h rimsky /branches/sparc/ Implemented input and output drivers for Niagara. Written in the old-fashion style (do not use the new DDI infrastructure nor the new keyboard driver). Anyway, tetris can be played.  
4068 5539 d 13 h rimsky /branches/sparc/kernel/arch/sparc64/src/trap/sun4v/ Fixed a stupid bug.  
4065 5540 d 12 h rimsky /branches/sparc/kernel/arch/sparc64/src/ minor cleanup  
4064 5540 d 13 h rimsky /branches/sparc/kernel/arch/sparc64/src/trap/sun4v/ Workaround for the bug which usually caused rewriting saved register window data on the uspace stack. More investigation needed.  
4063 5540 d 13 h rimsky /branches/sparc/uspace/lib/libc/arch/sparc64/include/ Fixed the bug which caused unexpected MMU misses. The fix breaks sun4u ports - this will be solved once the sun4v is integrated with the new configuration mechanism, which allows to define common options for both kernel and uspace.  
3993 5547 d 12 h rimsky /branches/sparc/kernel/ Implemented preemptible trap handler for userspace (including syscalls - did not forget enabling interrupts for them) and the ralated stuff. Implemented handlers of instruction/data MMU miss/protection. Now some userspace tasks are run; there are, however, still some bugs causing unexpected data MMU misses.  
3864 5568 d 13 h rimsky /branches/sparc/kernel/arch/sparc64/src/sun4v/ Allocated bigger memory block for the Machine Description. This was the problem which prevented running HelenOS on real Niagara. Now all kernel tests except for 'slab2' pass on real Niagara.  
3863 5569 d 12 h rimsky /branches/sparc/ Simics machine: modifications needed to run userspace (the next step will be to implement the trap handler for uspace); real machine: small fixes, after them the machine passes some parts of the initialization, but fails to determine CPU frequency (probably due to a different format of Machine Description).  
3862 5572 d 12 h rimsky /branches/sparc/kernel/ Changed the structure of header files, which have sun4u and sun4v versions. Implemented some sun4v TSB functions.  
3835 5577 d 12 h rimsky /branches/sparc/kernel/arch/sparc64/ Niagara: Implemented (and debugged) installing identity mapping for kernel. Now all the kernel tests pass on Simics.  
3817 5585 d 12 h rimsky /branches/sparc/kernel/ Progress on Niagara: Commented out portions of mm, which are not required for kernel threads (temporarily). Scheduler is working. Implemented a driver of hypervisor's standard input. Kernel console is usable.  
3801 5589 d 14 h rimsky /branches/sparc/kernel/arch/sparc64/src/trap/sun4v/ Minor fixes in the preemptible trap handler.  
3798 5590 d 12 h rimsky /branches/sparc/kernel/ Implemented preemptible trap handler for sun4v for trapping from kernel (not userspace). Not properly tested/debugged yet. HelenOS now reaches the as_install_arch function (where it, of course, fails).  
3783 5602 d 13 h rimsky /branches/sparc/kernel/arch/sparc64/ Machine description traversal implemented. Now used to detect CPU frequency.  
3771 5605 d 13 h rimsky /branches/sparc/kernel/arch/sparc64/ Forgotten files comitted to repository.  
3770 5605 d 13 h rimsky /branches/sparc/ Working on Niagara port - TLB initialization, MMU fault status area initialization, hypercall enhancement, modified tick.c so that the (hyperprivileged) TICK register does not have to be accessed. Now the initialization phase proceeds, but some parts of it are omitted for now (e.g. CPU initialization).  

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