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Rev Age Author Path Log message Diff Changes
400 6968 d 8 h jermar /SPARTAN/trunk/ Finalize mapping1 test.
Record omitted excMod bug in msim.		  
/SPARTAN/trunk/doc/BUGS_FOUND
/SPARTAN/trunk/test/mm/mapping1/test.c
399 6968 d 18 h jermar /SPARTAN/trunk/ mips32 memory management work.
TLB exceptions seem to be working on at least simics.
msim handles TLB Refill and TLB Invalid exceptions well,
but seems to skip writes to the mapped addressies in mm
mapping test #1 (the data is not written and exception
is not triggered).		  
/SPARTAN/trunk/arch/mips32/include/mm/tlb.h
/SPARTAN/trunk/arch/mips32/src/mm/tlb.c
/SPARTAN/trunk/test/mm/mapping1/test.c
397 6969 d 8 h jermar /SPARTAN/trunk/ Small changes to mips32 mm.
Small changes in mm mapping test #1.		  
/SPARTAN/trunk/Makefile.config
/SPARTAN/trunk/arch/mips32/src/mm/tlb.c
/SPARTAN/trunk/arch/mips32/src/mm/vm.c
/SPARTAN/trunk/test/mm/mapping1/test.c
396 6970 d 5 h jermar /SPARTAN/trunk/ Add mm/mapping1 test.
(Will not make it past TLB Invalid exception on mips32.)
Fixes in asid.c.
Make TLB register types union with __u32 value.
Implement tlb_invalidate() for mips32.
(TLB invalidation and shootdown path will have to be revised.)		  
/SPARTAN/trunk/test/mm
/SPARTAN/trunk/test/mm/mapping1
/SPARTAN/trunk/test/mm/mapping1/test.c
/SPARTAN/trunk/Makefile.config
/SPARTAN/trunk/arch/ia32/src/mm/tlb.c
/SPARTAN/trunk/arch/mips32/include/mm/asid.h
/SPARTAN/trunk/arch/mips32/include/mm/tlb.h
/SPARTAN/trunk/arch/mips32/src/mm/asid.c
/SPARTAN/trunk/arch/mips32/src/mm/tlb.c
/SPARTAN/trunk/arch/mips32/src/mm/vm.c
/SPARTAN/trunk/include/mm/tlb.h