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Rev	Age	Author	Path	Log message
903	6828 d 0 h	jermar	/kernel/trunk/arch/ia64/	ia64 work. Add code needed for running multiple address spaces and location of kernel stack after switch from userspace.
902	6829 d 5 h	jermar	/kernel/trunk/	ia64 work. More capable TLB miss handlers. The ia64 kernel now passes mm/mapping1 test. Fix generic hash table to properly initialize lists. Change page_ht() to properly initialize inserted PTE's. Change format of generic page hash table PTE's.
901	6829 d 6 h	jermar	/kernel/trunk/arch/	ia64 work. Provide PA2KA(identity) mapping for kernel data references via Alternate Data TLB Fault handler. Add before_thread_runs_arch() that maps kstack, if necessary. Add easy to use dtlb_mapping_insert() for comfortable insertion of kernel data mappings.
900	6830 d 0 h	jermar	/kernel/trunk/arch/ia64/	ia64 work. Proper TLB fault handlers' headers and prototypes. PFN 0 needs no longer be marked unavailable to frame allocator.
899	6830 d 1 h	jermar	/kernel/trunk/arch/	ia64 work. Add dummy TLB fault handlers. Improve code reuse in arch/mm/tlb.c.
879	6832 d 22 h	vana	/kernel/trunk/arch/ia64/	Itanium kernel page extended to maximum (256M) repaired RR manipulation functions, paging setuping function and added some comments.
870	6835 d 18 h	vana	/kernel/trunk/arch/ia64/	Removed forgoten debug function and reverted my mistake
869	6835 d 18 h	vana	/kernel/trunk/	Uaaaaaaa ;-) Itanium Paging !!!!!! ;-)
819	6849 d 21 h	vana	/kernel/trunk/arch/ia64/	TR tlb filling functions
818	6850 d 0 h	vana	/kernel/trunk/arch/ia64/	IA-64 TLB filling functions for dynamic tlb filling (TC tlb).
792	6852 d 3 h	jermar	/kernel/trunk/	Page hash table architectures now use generic hash table to manage mappings.
763	6856 d 2 h	jermar	/kernel/trunk/	Modify frame.h to use shifting instead of multiplication and division. Define FRAME_WIDTH for all architectures.
756	6857 d 18 h	jermar	/kernel/trunk/	Memory management work. Remove the last (i.e. 'root') argument from page_mapping_insert() and page_mapping_find(). Page table address is now extracted from the first (i.e. 'as') argument. Add a lot of infrastructure to make the above possible. sparc64 is now broken, most likely because of insufficient identity mapping of physical memory.
753	6859 d 1 h	jermar	/kernel/trunk/	Convert ASID management of ia64 to ASID FIFO mechanism. 18-bit RIDs are supported.
751	6859 d 3 h	jermar	/kernel/trunk/arch/ia64/	Fix initialization of pta.base on ia64.
749	6861 d 1 h	jermar	/kernel/trunk/arch/ia64/	ia64 virtual address translation subsystem update.
748	6862 d 1 h	jermar	/kernel/trunk/arch/ia64/	First HT_HASH_ARCH implementation for ia64.
747	6862 d 19 h	jermar	/kernel/trunk/	ia64 work. Add nice wrappers for thash and ttag instructions. Add nice wrappers for accessing reion registers and PTA. Fix set_vhpt_environment(). Allocate and initialize page_ht (a.k.a. VHPT). Add missing header to sparc64. Remove excessive header from debug.h.
746	6863 d 3 h	jermar	/kernel/trunk/	Page hash table modifications.
741	6864 d 21 h	jermar	/kernel/trunk/	Unlock address space prior TLB shootdown in get_asid() to unify the locking order among mips32, sparc64 and ia64. Add ASID_STEALING_ENABLED macro to disable the stealing part on ia64 in a clean way.

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