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Rev Age Author Path Log message Diff
2250 6265 d 16 h jermar /trunk/boot/ Fix ticket #31.  
2249 6267 d 13 h jelen /branches/fs/boot/arch/mips32/loader/ configuration with ramdisk  
2248 6267 d 13 h jelen /branches/fs/uspace/ Connecting services cat -> fs -> rd  
2247 6267 d 13 h jelen /branches/fs/ A new "cat" task to test "fs" (read a file and dump it onto the console)  
2246 6267 d 13 h jelen /branches/fs/kernel/generic/src/lib/ Go back to checking data size against frame size  
2245 6268 d 0 h stepan /branches/arm/kernel/arch/arm32/ irq dispatching
gxemul irq controller and timer "drivers"		  
2244 6268 d 4 h kebrt /branches/arm/kernel/arch/mips32/include/mm/ page has 16KB (ONE_FRAME used instead of FOUR_FRAMES)  
2243 6268 d 15 h kebrt /branches/arm/kernel/arch/arm32/ last_frame variable added (as in other archs), kernel page table created (not yet used)  
2242 6268 d 16 h kebrt /branches/arm/kernel/ ARM has 16kB first level page table, so PTL0..3_SIZE constants added to frame_alloc and all achitectures  
2241 6268 d 17 h kebrt /branches/arm/ comments & code standards & typo  
2240 6268 d 23 h jancik /branches/arm/kernel/arch/arm32/include/ Alf: reg r9 forgotten  
2239 6269 d 8 h jancik /branches/arm/boot/arch/arm32/loader/  
2238 6269 d 15 h kebrt /branches/arm/kernel/arch/arm32/ refactoring & comments & code standards  
2237 6269 d 15 h jermar /trunk/boot/arch/sparc64/silo/ Upgrade SILO to 1.4.13.  
2236 6269 d 17 h kebrt /branches/arm/boot/arch/arm32/loader/ refactoring & comments & code standards  
2235 6269 d 18 h stepan /branches/arm/kernel/arch/arm32/ exception handling
simple interrupt processing		  
2234 6270 d 18 h jancik /branches/arm/boot/arch/arm32/loader/ Alf: stabni kultura  
2233 6271 d 15 h decky /trunk/kernel/arch/ use the hlt instruction more properly  
2232 6271 d 16 h decky /trunk/kernel/arch/mips32/src/ add support for halt/reboot in MSIM  
2231 6271 d 20 h jermar /trunk/kernel/arch/sparc64/ Fix a nasty bug in the TLB miss handlers on sparc64.
After we no longer lock the kernel stack in the DTLB,
there is a real danger of nested DTLB misses. The nested
miss can very easily clobber the DTLB Tag Access register.
Therefore, the original miss may not read this register, but
it has to receive its value as an argument. The argument
value is saved in the trap table when it is guaranteed that
the nested TLB miss will not occur.		  

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