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1290 6677 d 16 h vana /kernel/trunk/arch/ VESA detection failure fix.

(Some headers)		  
1210 6691 d 17 h vana /kernel/trunk/ Incomplete VHPT walker support for Itanium  
1138 6716 d 13 h jermar /kernel/trunk/ CPU stacks must have two frames on ia64.
Make sure both thread stack frames are mapped in before_thread_runs_arch().
Take STACK_FRAMES into account during kernel memory layout initialization in main_bsp().		  
1108 6721 d 7 h jermar /kernel/trunk/ Small PTE_* macros and SET_PTL0_ADDRESS macro changes.  
1070 6726 d 20 h jermar /kernel/trunk/ More checks for address space area conflicts.  
967 6729 d 19 h palkovsky /kernel/trunk/ Allowed userspace to include page.h.  
958 6730 d 10 h jermar /kernel/trunk/ Nicer ia32 interrupt handlers and structures holding interrupted context data.
Unify the name holding interrupted context data on all architectures to be istate.		  
945 6731 d 8 h vana /kernel/trunk/arch/ia64/  
944 6731 d 9 h vana /kernel/trunk/ Itanium tlb_invalidate_pages  
940 6731 d 11 h jermar /kernel/trunk/ Get rid of unneeded macros.
Their functionality has been replaced by the ELF loader.		  
935 6731 d 12 h vana /kernel/trunk/ Two frame stack (standard stack + RSE) on Itanium  
919 6734 d 17 h jermar /kernel/trunk/ ia64 work.
Changes to make userspace work (kernel part).
Use ski.conf from contrib directory to run Ski.

There is actually no appropriate syscall handler yet.		  
915 6736 d 19 h jermar /kernel/trunk/arch/ia64/ ia64 work.
- Another item had to be allocated on stack to remember new value written to ar.bspstore.
Fix heavyweight interruption handler to calculate RSC.loadrs from the new value of ar.bspstore
instead from the old one.
Uncomment instructions switching ar.bspstore.
- Configure kernel with 512M of memory.		  
911 6738 d 13 h jermar /kernel/trunk/arch/ia64/ ia64 work.

Change heavyweight interrupt handler to use bank 0 registers instead of AR.KR0 and AR.KR1.
This prevents userspace from the possibility to see what addresses are being used by kernel.

Store kernel stack address in bank 0 r23 instead of AR.KR7. Again, userspace will not be
able to read the address of its kernel stack.

Increase FRAME_SIZE to 64K as this is the first supported page size in which will fit
thread's combined register and memory stack. (RSE can write out as many as 16K.)		  
903 6741 d 12 h jermar /kernel/trunk/arch/ia64/ ia64 work.
Add code needed for running multiple address spaces and location of kernel stack
after switch from userspace.		  
902 6742 d 17 h jermar /kernel/trunk/ ia64 work.
More capable TLB miss handlers.
The ia64 kernel now passes mm/mapping1 test.

Fix generic hash table to properly initialize lists.

Change page_ht() to properly initialize inserted PTE's.
Change format of generic page hash table PTE's.		  
901 6742 d 19 h jermar /kernel/trunk/arch/ ia64 work.
Provide PA2KA(identity) mapping for kernel data references via Alternate Data TLB Fault handler.
Add before_thread_runs_arch() that maps kstack, if necessary.
Add easy to use dtlb_mapping_insert() for comfortable insertion of kernel data mappings.		  
900 6743 d 12 h jermar /kernel/trunk/arch/ia64/ ia64 work.
Proper TLB fault handlers' headers and prototypes.
PFN 0 needs no longer be marked unavailable to frame allocator.		  
899 6743 d 13 h jermar /kernel/trunk/arch/ ia64 work.
Add dummy TLB fault handlers.
Improve code reuse in arch/mm/tlb.c.		  
879 6746 d 10 h vana /kernel/trunk/arch/ia64/ Itanium kernel page extended to maximum (256M) repaired RR manipulation functions, paging setuping function and added some comments.  

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