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Rev Age Author Path Log message Diff
1511 6730 d 16 h palkovsky /kernel/trunk/arch/ Remove __address from include file included by uspace  
1290 6758 d 17 h vana /kernel/trunk/arch/ VESA detection failure fix.

(Some headers)		  
1210 6772 d 18 h vana /kernel/trunk/ Incomplete VHPT walker support for Itanium  
1138 6797 d 14 h jermar /kernel/trunk/ CPU stacks must have two frames on ia64.
Make sure both thread stack frames are mapped in before_thread_runs_arch().
Take STACK_FRAMES into account during kernel memory layout initialization in main_bsp().		  
1108 6802 d 8 h jermar /kernel/trunk/ Small PTE_* macros and SET_PTL0_ADDRESS macro changes.  
1070 6807 d 20 h jermar /kernel/trunk/ More checks for address space area conflicts.  
967 6810 d 20 h palkovsky /kernel/trunk/ Allowed userspace to include page.h.  
958 6811 d 10 h jermar /kernel/trunk/ Nicer ia32 interrupt handlers and structures holding interrupted context data.
Unify the name holding interrupted context data on all architectures to be istate.		  
945 6812 d 9 h vana /kernel/trunk/arch/ia64/  
944 6812 d 10 h vana /kernel/trunk/ Itanium tlb_invalidate_pages  
940 6812 d 12 h jermar /kernel/trunk/ Get rid of unneeded macros.
Their functionality has been replaced by the ELF loader.		  
935 6812 d 13 h vana /kernel/trunk/ Two frame stack (standard stack + RSE) on Itanium  
919 6815 d 18 h jermar /kernel/trunk/ ia64 work.
Changes to make userspace work (kernel part).
Use ski.conf from contrib directory to run Ski.

There is actually no appropriate syscall handler yet.		  
915 6817 d 20 h jermar /kernel/trunk/arch/ia64/ ia64 work.
- Another item had to be allocated on stack to remember new value written to ar.bspstore.
Fix heavyweight interruption handler to calculate RSC.loadrs from the new value of ar.bspstore
instead from the old one.
Uncomment instructions switching ar.bspstore.
- Configure kernel with 512M of memory.		  
911 6819 d 14 h jermar /kernel/trunk/arch/ia64/ ia64 work.

Change heavyweight interrupt handler to use bank 0 registers instead of AR.KR0 and AR.KR1.
This prevents userspace from the possibility to see what addresses are being used by kernel.

Store kernel stack address in bank 0 r23 instead of AR.KR7. Again, userspace will not be
able to read the address of its kernel stack.

Increase FRAME_SIZE to 64K as this is the first supported page size in which will fit
thread's combined register and memory stack. (RSE can write out as many as 16K.)		  
903 6822 d 13 h jermar /kernel/trunk/arch/ia64/ ia64 work.
Add code needed for running multiple address spaces and location of kernel stack
after switch from userspace.		  
902 6823 d 18 h jermar /kernel/trunk/ ia64 work.
More capable TLB miss handlers.
The ia64 kernel now passes mm/mapping1 test.

Fix generic hash table to properly initialize lists.

Change page_ht() to properly initialize inserted PTE's.
Change format of generic page hash table PTE's.		  
901 6823 d 19 h jermar /kernel/trunk/arch/ ia64 work.
Provide PA2KA(identity) mapping for kernel data references via Alternate Data TLB Fault handler.
Add before_thread_runs_arch() that maps kstack, if necessary.
Add easy to use dtlb_mapping_insert() for comfortable insertion of kernel data mappings.		  
900 6824 d 13 h jermar /kernel/trunk/arch/ia64/ ia64 work.
Proper TLB fault handlers' headers and prototypes.
PFN 0 needs no longer be marked unavailable to frame allocator.		  
899 6824 d 14 h jermar /kernel/trunk/arch/ ia64 work.
Add dummy TLB fault handlers.
Improve code reuse in arch/mm/tlb.c.		  
879 6827 d 11 h vana /kernel/trunk/arch/ia64/ Itanium kernel page extended to maximum (256M) repaired RR manipulation functions, paging setuping function and added some comments.  
870 6830 d 7 h vana /kernel/trunk/arch/ia64/ Removed forgoten debug function and reverted my mistake  
869 6830 d 7 h vana /kernel/trunk/ Uaaaaaaa ;-) Itanium Paging !!!!!! ;-)  
819 6844 d 10 h vana /kernel/trunk/arch/ia64/ TR tlb filling functions  
818 6844 d 13 h vana /kernel/trunk/arch/ia64/ IA-64 TLB filling functions for dynamic tlb filling (TC tlb).  
792 6846 d 16 h jermar /kernel/trunk/ Page hash table architectures now use generic hash table to manage
mappings.		  
763 6850 d 15 h jermar /kernel/trunk/ Modify frame.h to use shifting instead of multiplication and division.
Define FRAME_WIDTH for all architectures.		  
756 6852 d 7 h jermar /kernel/trunk/ Memory management work.
Remove the last (i.e. 'root') argument from page_mapping_insert() and page_mapping_find().
Page table address is now extracted from the first (i.e. 'as') argument.
Add a lot of infrastructure to make the above possible.
sparc64 is now broken, most likely because of insufficient identity mapping of physical memory.		  
753 6853 d 14 h jermar /kernel/trunk/ Convert ASID management of ia64 to ASID FIFO mechanism.
18-bit RIDs are supported.		  
751 6853 d 16 h jermar /kernel/trunk/arch/ia64/ Fix initialization of pta.base on ia64.  
749 6855 d 14 h jermar /kernel/trunk/arch/ia64/ ia64 virtual address translation subsystem update.  
748 6856 d 14 h jermar /kernel/trunk/arch/ia64/ First HT_HASH_ARCH implementation for ia64.  
747 6857 d 8 h jermar /kernel/trunk/ ia64 work.
Add nice wrappers for thash and ttag instructions.
Add nice wrappers for accessing reion registers and PTA.
Fix set_vhpt_environment().
Allocate and initialize page_ht (a.k.a. VHPT).

Add missing header to sparc64.
Remove excessive header from debug.h.		  
746 6857 d 16 h jermar /kernel/trunk/ Page hash table modifications.  
741 6859 d 10 h jermar /kernel/trunk/ Unlock address space prior TLB shootdown in get_asid() to unify
the locking order among mips32, sparc64 and ia64.

Add ASID_STEALING_ENABLED macro to disable the stealing part on ia64
in a clean way.		  
740 6859 d 16 h jermar /kernel/trunk/ ia64 ASID management code (not tested).  
730 6862 d 13 h jermar /kernel/trunk/ Finalize ASID management for sparc64 and mips32 by making use of FIFO queue of ASIDs.  
727 6864 d 8 h jermar /kernel/trunk/ New ASID management subsystem (initial work, more is required).
Some TLB invalidation changes.		  
715 6868 d 12 h vana /kernel/trunk/arch/ia64/ VHPT setup to be able to use ttag and thash instructions  
710 6868 d 15 h vana /kernel/trunk/arch/ia64/include/mm/ VHPT entry