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  1. /*
  2.  * Copyright (C) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #include <arch/mm/tlb.h>
  30. #include <mm/tlb.h>
  31. #include <arch/mm/frame.h>
  32. #include <arch/mm/page.h>
  33. #include <arch/mm/mmu.h>
  34. #include <print.h>
  35. #include <arch/types.h>
  36. #include <typedefs.h>
  37. #include <config.h>
  38. #include <arch/trap/trap.h>
  39. #include <panic.h>
  40.  
  41. /** Initialize ITLB and DTLB.
  42.  *
  43.  * The goal of this function is to disable MMU
  44.  * so that both TLBs can be purged and new
  45.  * kernel 4M locked entry can be installed.
  46.  * After TLB is initialized, MMU is enabled
  47.  * again.
  48.  *
  49.  * Switching MMU off imposes the requirement for
  50.  * the kernel to run in identity mapped environment.
  51.  */
  52. void tlb_arch_init(void)
  53. {
  54.     tlb_tag_access_reg_t tag;
  55.     tlb_data_t data;
  56.     frame_address_t fr;
  57.     page_address_t pg;
  58.  
  59.     fr.address = config.base;
  60.     pg.address = config.base;
  61.  
  62.     immu_disable();
  63.     dmmu_disable();
  64.    
  65.     /*
  66.      * We do identity mapping of 4M-page at 4M.
  67.      */
  68.     tag.value = 0;
  69.     tag.vpn = pg.vpn;
  70.  
  71.     itlb_tag_access_write(tag.value);
  72.     dtlb_tag_access_write(tag.value);
  73.  
  74.     data.value = 0;
  75.     data.v = true;
  76.     data.size = PAGESIZE_4M;
  77.     data.pfn = fr.pfn;
  78.     data.l = true;
  79.     data.cp = 1;
  80.     data.cv = 1;
  81.     data.p = true;
  82.     data.w = true;
  83.     data.g = true;
  84.  
  85.     itlb_data_in_write(data.value);
  86.     dtlb_data_in_write(data.value);
  87.  
  88.     /*
  89.      * Register window traps can occur before MMU is enabled again.
  90.      * This ensures that any such traps will be handled from
  91.      * kernel identity mapped trap handler.
  92.      */
  93.     trap_switch_trap_table();
  94.    
  95.     tlb_invalidate_all();
  96.  
  97.     dmmu_enable();
  98.     immu_enable();
  99. }
  100.  
  101. /** ITLB miss handler. */
  102. void fast_instruction_access_mmu_miss(void)
  103. {
  104.     panic("%s\n", __FUNCTION__);
  105. }
  106.  
  107. /** DTLB miss handler. */
  108. void fast_data_access_mmu_miss(void)
  109. {
  110.     panic("%s\n", __FUNCTION__);
  111. }
  112.  
  113. /** DTLB protection fault handler. */
  114. void fast_data_access_protection(void)
  115. {
  116.     panic("%s\n", __FUNCTION__);
  117. }
  118.  
  119. /** Print contents of both TLBs. */
  120. void tlb_print(void)
  121. {
  122.     int i;
  123.     tlb_data_t d;
  124.     tlb_tag_read_reg_t t;
  125.    
  126.     printf("I-TLB contents:\n");
  127.     for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
  128.         d.value = itlb_data_access_read(i);
  129.         t.value = itlb_tag_read_read(i);
  130.        
  131.         printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
  132.             i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
  133.     }
  134.  
  135.     printf("D-TLB contents:\n");
  136.     for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
  137.         d.value = dtlb_data_access_read(i);
  138.         t.value = dtlb_tag_read_read(i);
  139.        
  140.         printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
  141.             i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
  142.     }
  143.  
  144. }
  145.  
  146. /** Invalidate all unlocked ITLB and DTLB entries. */
  147. void tlb_invalidate_all(void)
  148. {
  149.     int i;
  150.     tlb_data_t d;
  151.     tlb_tag_read_reg_t t;
  152.  
  153.     for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
  154.         d.value = itlb_data_access_read(i);
  155.         if (!d.l) {
  156.             t.value = itlb_tag_read_read(i);
  157.             d.v = false;
  158.             itlb_tag_access_write(t.value);
  159.             itlb_data_access_write(i, d.value);
  160.         }
  161.     }
  162.    
  163.     for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
  164.         d.value = dtlb_data_access_read(i);
  165.         if (!d.l) {
  166.             t.value = dtlb_tag_read_read(i);
  167.             d.v = false;
  168.             dtlb_tag_access_write(t.value);
  169.             dtlb_data_access_write(i, d.value);
  170.         }
  171.     }
  172.    
  173. }
  174.  
  175. /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
  176.  *
  177.  * @param asid Address Space ID.
  178.  */
  179. void tlb_invalidate_asid(asid_t asid)
  180. {
  181.     /* TODO: write asid to some Context register and encode the register in second parameter below. */
  182.     itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
  183.     dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
  184. }
  185.  
  186. /** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
  187.  *
  188.  * @param asid Address Space ID.
  189.  * @param page First page which to sweep out from ITLB and DTLB.
  190.  * @param cnt Number of ITLB and DTLB entries to invalidate.
  191.  */
  192. void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
  193. {
  194.     int i;
  195.    
  196.     for (i = 0; i < cnt; i++) {
  197.         /* TODO: write asid to some Context register and encode the register in second parameter below. */
  198.         itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
  199.         dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
  200.     }
  201. }
  202.