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  1. /*
  2.  * Copyright (C) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #ifndef __sparc64_TLB_H__
  30. #define __sparc64_TLB_H__
  31.  
  32. #include <arch/mm/tte.h>
  33. #include <arch/mm/mmu.h>
  34. #include <arch/mm/page.h>
  35. #include <arch/asm.h>
  36. #include <arch/barrier.h>
  37. #include <arch/types.h>
  38. #include <typedefs.h>
  39.  
  40. #define ITLB_ENTRY_COUNT        64
  41. #define DTLB_ENTRY_COUNT        64
  42.  
  43. /** Page sizes. */
  44. #define PAGESIZE_8K 0
  45. #define PAGESIZE_64K    1
  46. #define PAGESIZE_512K   2
  47. #define PAGESIZE_4M 3
  48.  
  49. /** I-/D-TLB Data In/Access Register type. */
  50. typedef tte_data_t tlb_data_t;
  51.  
  52. /** I-/D-TLB Data Access Address in Alternate Space. */
  53. union tlb_data_access_addr {
  54.     __u64 value;
  55.     struct {
  56.         __u64 : 55;
  57.         unsigned tlb_entry : 6;
  58.         unsigned : 3;
  59.     } __attribute__ ((packed));
  60. };
  61. typedef union tlb_data_access_addr tlb_data_access_addr_t;
  62. typedef union tlb_data_access_addr tlb_tag_read_addr_t;
  63.  
  64. /** I-/D-TLB Tag Read Register. */
  65. union tlb_tag_read_reg {
  66.     __u64 value;
  67.     struct {
  68.         __u64 vpn : 51;     /**< Virtual Address bits 63:13. */
  69.         unsigned context : 13;  /**< Context identifier. */
  70.     } __attribute__ ((packed));
  71. };
  72. typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
  73. typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
  74.  
  75. /** TLB Demap Operation types. */
  76. #define TLB_DEMAP_PAGE      0
  77. #define TLB_DEMAP_CONTEXT   1
  78.  
  79. /** TLB Demap Operation Context register encodings. */
  80. #define TLB_DEMAP_PRIMARY   0
  81. #define TLB_DEMAP_SECONDARY 1
  82. #define TLB_DEMAP_NUCLEUS   2
  83.  
  84. /** TLB Demap Operation Address. */
  85. union tlb_demap_addr {
  86.     __u64 value;
  87.     struct {
  88.         __u64 vpn: 51;      /**< Virtual Address bits 63:13. */
  89.         unsigned : 6;       /**< Ignored. */
  90.         unsigned type : 1;  /**< The type of demap operation. */
  91.         unsigned context : 2;   /**< Context register selection. */
  92.         unsigned : 4;       /**< Zero. */
  93.     } __attribute__ ((packed));
  94. };
  95. typedef union tlb_demap_addr tlb_demap_addr_t;
  96.  
  97. /** Read IMMU TLB Data Access Register.
  98.  *
  99.  * @param entry TLB Entry index.
  100.  *
  101.  * @return Current value of specified IMMU TLB Data Access Register.
  102.  */
  103. static inline __u64 itlb_data_access_read(index_t entry)
  104. {
  105.     tlb_data_access_addr_t reg;
  106.    
  107.     reg.value = 0;
  108.     reg.tlb_entry = entry;
  109.     return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
  110. }
  111.  
  112. /** Write IMMU TLB Data Access Register.
  113.  *
  114.  * @param entry TLB Entry index.
  115.  * @param value Value to be written.
  116.  */
  117. static inline __u64 itlb_data_access_write(index_t entry, __u64 value)
  118. {
  119.     tlb_data_access_addr_t reg;
  120.    
  121.     reg.value = 0;
  122.     reg.tlb_entry = entry;
  123.     asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
  124.     flush();
  125. }
  126.  
  127. /** Read DMMU TLB Data Access Register.
  128.  *
  129.  * @param entry TLB Entry index.
  130.  *
  131.  * @return Current value of specified DMMU TLB Data Access Register.
  132.  */
  133. static inline __u64 dtlb_data_access_read(index_t entry)
  134. {
  135.     tlb_data_access_addr_t reg;
  136.    
  137.     reg.value = 0;
  138.     reg.tlb_entry = entry;
  139.     return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
  140. }
  141.  
  142. /** Write DMMU TLB Data Access Register.
  143.  *
  144.  * @param entry TLB Entry index.
  145.  * @param value Value to be written.
  146.  */
  147. static inline __u64 dtlb_data_access_write(index_t entry, __u64 value)
  148. {
  149.     tlb_data_access_addr_t reg;
  150.    
  151.     reg.value = 0;
  152.     reg.tlb_entry = entry;
  153.     asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
  154.     flush();
  155. }
  156.  
  157. /** Read IMMU TLB Tag Read Register.
  158.  *
  159.  * @param entry TLB Entry index.
  160.  *
  161.  * @return Current value of specified IMMU TLB Tag Read Register.
  162.  */
  163. static inline __u64 itlb_tag_read_read(index_t entry)
  164. {
  165.     tlb_tag_read_addr_t tag;
  166.  
  167.     tag.value = 0;
  168.     tag.tlb_entry = entry;
  169.     return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
  170. }
  171.  
  172. /** Read DMMU TLB Tag Read Register.
  173.  *
  174.  * @param entry TLB Entry index.
  175.  *
  176.  * @return Current value of specified DMMU TLB Tag Read Register.
  177.  */
  178. static inline __u64 dtlb_tag_read_read(index_t entry)
  179. {
  180.     tlb_tag_read_addr_t tag;
  181.  
  182.     tag.value = 0;
  183.     tag.tlb_entry = entry;
  184.     return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
  185. }
  186.  
  187. /** Write IMMU TLB Tag Access Register.
  188.  *
  189.  * @param v Value to be written.
  190.  */
  191. static inline void itlb_tag_access_write(__u64 v)
  192. {
  193.     asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
  194.     flush();
  195. }
  196.  
  197. /** Write DMMU TLB Tag Access Register.
  198.  *
  199.  * @param v Value to be written.
  200.  */
  201. static inline void dtlb_tag_access_write(__u64 v)
  202. {
  203.     asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
  204.     flush();
  205. }
  206.  
  207. /** Write IMMU TLB Data in Register.
  208.  *
  209.  * @param v Value to be written.
  210.  */
  211. static inline void itlb_data_in_write(__u64 v)
  212. {
  213.     asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
  214.     flush();
  215. }
  216.  
  217. /** Write DMMU TLB Data in Register.
  218.  *
  219.  * @param v Value to be written.
  220.  */
  221. static inline void dtlb_data_in_write(__u64 v)
  222. {
  223.     asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
  224.     flush();
  225. }
  226.  
  227. /** Perform IMMU TLB Demap Operation.
  228.  *
  229.  * @param type Selects between context and page demap.
  230.  * @param context_encoding Specifies which Context register has Context ID for demap.
  231.  * @param page Address which is on the page to be demapped.
  232.  */
  233. static inline void itlb_demap(int type, int context_encoding, __address page)
  234. {
  235.     tlb_demap_addr_t da;
  236.     page_address_t pg;
  237.    
  238.     da.value = 0;
  239.     pg.address = page;
  240.    
  241.     da.type = type;
  242.     da.context = context_encoding;
  243.     da.vpn = pg.vpn;
  244.    
  245.     asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
  246.     flush();
  247. }
  248.  
  249. /** Perform DMMU TLB Demap Operation.
  250.  *
  251.  * @param type Selects between context and page demap.
  252.  * @param context_encoding Specifies which Context register has Context ID for demap.
  253.  * @param page Address which is on the page to be demapped.
  254.  */
  255. static inline void dtlb_demap(int type, int context_encoding, __address page)
  256. {
  257.     tlb_demap_addr_t da;
  258.     page_address_t pg;
  259.    
  260.     da.value = 0;
  261.     pg.address = page;
  262.    
  263.     da.type = type;
  264.     da.context = context_encoding;
  265.     da.vpn = pg.vpn;
  266.    
  267.     asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
  268.     flush();
  269. }
  270.  
  271. #endif
  272.