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  1. /*
  2.  * Copyright (C) 2003-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #include <arch/interrupt.h>
  30. #include <arch/types.h>
  31. #include <arch.h>
  32. #include <arch/cp0.h>
  33. #include <time/clock.h>
  34. #include <panic.h>
  35.  
  36. pri_t cpu_priority_high(void)
  37. {
  38.     pri_t pri = (pri_t) cp0_status_read();
  39.     cp0_status_write(pri & ~cp0_status_ie_enabled_bit);
  40.     return pri;
  41. }
  42.  
  43. pri_t cpu_priority_low(void)
  44. {
  45.     pri_t pri = (pri_t) cp0_status_read();
  46.     cp0_status_write(pri | cp0_status_ie_enabled_bit);
  47.     return pri;
  48. }
  49.  
  50. void cpu_priority_restore(pri_t pri)
  51. {
  52.     cp0_status_write(cp0_status_read() | (pri & cp0_status_ie_enabled_bit));
  53. }
  54.  
  55. pri_t cpu_priority_read(void)
  56. {
  57.     return cp0_status_read();
  58. }
  59.  
  60.  
  61. void interrupt(void)
  62. {
  63.     __u32 cause;
  64.     int i;
  65.    
  66.     /* decode interrupt number and process the interrupt */
  67.     cause = (cp0_cause_read() >> 8) &0xff;
  68.    
  69.     for (i = 0; i < 8; i++) {
  70.         if (cause & (1 << i)) {
  71.             switch (i) {
  72.                 case 0: /* SW0 - Software interrupt 0 */
  73.                     cp0_cause_write(cause & ~(1 << 8)); /* clear SW0 interrupt */
  74.                     break;
  75.                 case 1: /* SW1 - Software interrupt 1 */
  76.                     cp0_cause_write(cause & ~(1 << 9)); /* clear SW1 interrupt */
  77.                     break;
  78.                 case 2: /* IRQ0 */
  79.                 case 3: /* IRQ1 */
  80.                 case 4: /* IRQ2 */
  81.                 case 5: /* IRQ3 */
  82.                 case 6: /* IRQ4 */
  83.                     panic("unhandled interrupt %d\n", i);
  84.                     break;
  85.                 case 7: /* Timer Interrupt */
  86.                     cp0_compare_write(cp0_compare_value); /* clear timer interrupt */
  87.                     /* start counting over again */
  88.                     cp0_count_write(0);
  89.                     clock();
  90.                     break;
  91.             }
  92.         }
  93.     }
  94.  
  95. }
  96.