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  1. /*
  2.  * Copyright (C) 2003-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29.  /** @addtogroup mips32interrupt
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #include <interrupt.h>
  36. #include <arch/interrupt.h>
  37. #include <arch/types.h>
  38. #include <arch.h>
  39. #include <arch/cp0.h>
  40. #include <time/clock.h>
  41. #include <arch/drivers/arc.h>
  42.  
  43. #include <ipc/sysipc.h>
  44.  
  45. /** Disable interrupts.
  46.  *
  47.  * @return Old interrupt priority level.
  48.  */
  49. ipl_t interrupts_disable(void)
  50. {
  51.     ipl_t ipl = (ipl_t) cp0_status_read();
  52.     cp0_status_write(ipl & ~cp0_status_ie_enabled_bit);
  53.     return ipl;
  54. }
  55.  
  56. /** Enable interrupts.
  57.  *
  58.  * @return Old interrupt priority level.
  59.  */
  60. ipl_t interrupts_enable(void)
  61. {
  62.     ipl_t ipl = (ipl_t) cp0_status_read();
  63.     cp0_status_write(ipl | cp0_status_ie_enabled_bit);
  64.     return ipl;
  65. }
  66.  
  67. /** Restore interrupt priority level.
  68.  *
  69.  * @param ipl Saved interrupt priority level.
  70.  */
  71. void interrupts_restore(ipl_t ipl)
  72. {
  73.     cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit));
  74. }
  75.  
  76. /** Read interrupt priority level.
  77.  *
  78.  * @return Current interrupt priority level.
  79.  */
  80. ipl_t interrupts_read(void)
  81. {
  82.     return cp0_status_read();
  83. }
  84.  
  85. /* TODO: This is SMP unsafe!!! */
  86. static unsigned long nextcount;
  87. /** Start hardware clock */
  88. static void timer_start(void)
  89. {
  90.     nextcount = cp0_compare_value + cp0_count_read();
  91.     cp0_compare_write(nextcount);
  92. }
  93.  
  94. static void timer_exception(int n, istate_t *istate)
  95. {
  96.     unsigned long drift;
  97.  
  98.     drift = cp0_count_read() - nextcount;
  99.     while (drift > cp0_compare_value) {
  100.         drift -= cp0_compare_value;
  101.         CPU->missed_clock_ticks++;
  102.     }
  103.     nextcount = cp0_count_read() + cp0_compare_value - drift;
  104.     cp0_compare_write(nextcount);
  105.     clock();
  106. }
  107.  
  108. static void swint0(int n, istate_t *istate)
  109. {
  110.     cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */
  111.     ipc_irq_send_notif(0);
  112. }
  113.  
  114. static void swint1(int n, istate_t *istate)
  115. {
  116.     cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */
  117.     ipc_irq_send_notif(1);
  118. }
  119.  
  120. /* Initialize basic tables for exception dispatching */
  121. void interrupt_init(void)
  122. {
  123.     int_register(TIMER_IRQ, "timer", timer_exception);
  124.     int_register(0, "swint0", swint0);
  125.     int_register(1, "swint1", swint1);
  126.     timer_start();
  127. }
  128.  
  129. static void ipc_int(int n, istate_t *istate)
  130. {
  131.     ipc_irq_send_notif(n-INT_OFFSET);
  132. }
  133.  
  134. /* Reregister irq to be IPC-ready */
  135. void irq_ipc_bind_arch(unative_t irq)
  136. {
  137.     /* Do not allow to redefine timer */
  138.     /* Swint0, Swint1 are already handled */
  139.     if (irq == TIMER_IRQ || irq < 2)
  140.         return;
  141.     int_register(irq, "ipc_int", ipc_int);
  142. }
  143.  
  144.  /** @}
  145.  */
  146.  
  147.