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  1. /*
  2.  * Copyright (C) 2003-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #include <interrupt.h>
  30. #include <arch/interrupt.h>
  31. #include <arch/types.h>
  32. #include <arch.h>
  33. #include <arch/cp0.h>
  34. #include <time/clock.h>
  35. #include <arch/drivers/arc.h>
  36.  
  37. #include <ipc/sysipc.h>
  38.  
  39. /** Disable interrupts.
  40.  *
  41.  * @return Old interrupt priority level.
  42.  */
  43. ipl_t interrupts_disable(void)
  44. {
  45.     ipl_t ipl = (ipl_t) cp0_status_read();
  46.     cp0_status_write(ipl & ~cp0_status_ie_enabled_bit);
  47.     return ipl;
  48. }
  49.  
  50. /** Enable interrupts.
  51.  *
  52.  * @return Old interrupt priority level.
  53.  */
  54. ipl_t interrupts_enable(void)
  55. {
  56.     ipl_t ipl = (ipl_t) cp0_status_read();
  57.     cp0_status_write(ipl | cp0_status_ie_enabled_bit);
  58.     return ipl;
  59. }
  60.  
  61. /** Restore interrupt priority level.
  62.  *
  63.  * @param ipl Saved interrupt priority level.
  64.  */
  65. void interrupts_restore(ipl_t ipl)
  66. {
  67.     cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit));
  68. }
  69.  
  70. /** Read interrupt priority level.
  71.  *
  72.  * @return Current interrupt priority level.
  73.  */
  74. ipl_t interrupts_read(void)
  75. {
  76.     return cp0_status_read();
  77. }
  78.  
  79. /* TODO: This is SMP unsafe!!! */
  80. static unsigned long nextcount;
  81. /** Start hardware clock */
  82. static void timer_start(void)
  83. {
  84.     nextcount = cp0_compare_value + cp0_count_read();
  85.     cp0_compare_write(nextcount);
  86. }
  87.  
  88. static void timer_exception(int n, istate_t *istate)
  89. {
  90.     unsigned long drift;
  91.  
  92.     drift = cp0_count_read() - nextcount;
  93.     while (drift > cp0_compare_value) {
  94.         drift -= cp0_compare_value;
  95.         CPU->missed_clock_ticks++;
  96.     }
  97.     nextcount = cp0_count_read() + cp0_compare_value - drift;
  98.     cp0_compare_write(nextcount);
  99.     clock();
  100. }
  101.  
  102. static void swint0(int n, istate_t *istate)
  103. {
  104.     cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */
  105.     ipc_irq_send_notif(0);
  106. }
  107.  
  108. static void swint1(int n, istate_t *istate)
  109. {
  110.     cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */
  111.     ipc_irq_send_notif(1);
  112. }
  113.  
  114. /* Initialize basic tables for exception dispatching */
  115. void interrupt_init(void)
  116. {
  117.     int_register(TIMER_IRQ, "timer", timer_exception);
  118.     int_register(0, "swint0", swint0);
  119.     int_register(1, "swint1", swint1);
  120.     timer_start();
  121. }
  122.  
  123. static void ipc_int(int n, istate_t *istate)
  124. {
  125.     ipc_irq_send_notif(n-INT_OFFSET);
  126. }
  127.  
  128. /* Reregister irq to be IPC-ready */
  129. void irq_ipc_bind_arch(__native irq)
  130. {
  131.     /* Do not allow to redefine timer */
  132.     /* Swint0, Swint1 are already handled */
  133.     if (irq == TIMER_IRQ || irq < 2)
  134.         return;
  135.     int_register(irq, "ipc_int", ipc_int);
  136. }
  137.