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  1. /*
  2.  * Copyright (C) 2003-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #ifndef __mips32_PAGE_H__
  30. #define __mips32_PAGE_H__
  31.  
  32. #define PAGE_WIDTH  FRAME_WIDTH
  33. #define PAGE_SIZE   FRAME_SIZE
  34.  
  35. #ifndef __ASM__
  36. #  define KA2PA(x)  (((__address) (x)) - 0x80000000)
  37. #  define PA2KA(x)  (((__address) (x)) + 0x80000000)
  38. #else
  39. #  define KA2PA(x)  ((x) - 0x80000000)
  40. #  define PA2KA(x)  ((x) + 0x80000000)
  41. #endif
  42.  
  43. /*
  44.  * Implementation of generic 4-level page table interface.
  45.  * NOTE: this implementation is under construction
  46.  *
  47.  * Page table layout:
  48.  * - 32-bit virtual addresses
  49.  * - Offset is 14 bits => pages are 16K long
  50.  * - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore 4 bytes long
  51.  * - PTE's replace EntryLo v (valid) bit with p (present) bit
  52.  * - PTE's use only one bit to distinguish between cacheable and uncacheable mappings
  53.  * - PTE's define soft_valid field to ensure there is at least one 1 bit even if the p bit is cleared
  54.  * - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable) and bit A (accessed)
  55.  * - PTL0 has 64 entries (6 bits)
  56.  * - PTL1 is not used
  57.  * - PTL2 is not used
  58.  * - PTL3 has 4096 entries (12 bits)
  59.  */
  60.  
  61. #define PTL0_ENTRIES_ARCH   64
  62. #define PTL1_ENTRIES_ARCH   0
  63. #define PTL2_ENTRIES_ARCH   0
  64. #define PTL3_ENTRIES_ARCH   4096
  65.  
  66. #define PTL0_INDEX_ARCH(vaddr)  ((vaddr)>>26)
  67. #define PTL1_INDEX_ARCH(vaddr)  0
  68. #define PTL2_INDEX_ARCH(vaddr)  0
  69. #define PTL3_INDEX_ARCH(vaddr)  (((vaddr)>>14)&0x3fff)
  70.  
  71. #define SET_PTL0_ADDRESS_ARCH(ptl0)
  72.  
  73. #define GET_PTL1_ADDRESS_ARCH(ptl0, i)      (((pte_t *)(ptl0))[(i)].pfn<<12)
  74. #define GET_PTL2_ADDRESS_ARCH(ptl1, i)      (ptl1)
  75. #define GET_PTL3_ADDRESS_ARCH(ptl2, i)      (ptl2)
  76. #define GET_FRAME_ADDRESS_ARCH(ptl3, i)     (((pte_t *)(ptl3))[(i)].pfn<<12)
  77.  
  78. #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)   (((pte_t *)(ptl0))[(i)].pfn = (a)>>12)
  79. #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
  80. #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
  81. #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)  (((pte_t *)(ptl3))[(i)].pfn = (a)>>12)
  82.  
  83. #define GET_PTL1_FLAGS_ARCH(ptl0, i)        get_pt_flags((pte_t *)(ptl0), (index_t)(i))
  84. #define GET_PTL2_FLAGS_ARCH(ptl1, i)        PAGE_PRESENT
  85. #define GET_PTL3_FLAGS_ARCH(ptl2, i)        PAGE_PRESENT
  86. #define GET_FRAME_FLAGS_ARCH(ptl3, i)       get_pt_flags((pte_t *)(ptl3), (index_t)(i))
  87.  
  88. #define SET_PTL1_FLAGS_ARCH(ptl0, i, x)     set_pt_flags((pte_t *)(ptl0), (index_t)(i), (x))
  89. #define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
  90. #define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
  91. #define SET_FRAME_FLAGS_ARCH(ptl3, i, x)    set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x))
  92.  
  93. #define PTE_VALID_ARCH(p)           (*((__u32 *) (p)) != 0)
  94.  
  95. #ifndef __ASM__
  96.  
  97. #include <arch/mm/tlb.h>
  98. #include <mm/page.h>
  99. #include <arch/mm/frame.h>
  100. #include <arch/types.h>
  101.  
  102. static inline int get_pt_flags(pte_t *pt, index_t i)
  103. {
  104.     pte_t *p = &pt[i];
  105.    
  106.     return (
  107.         (p->cacheable<<PAGE_CACHEABLE_SHIFT) |
  108.         ((!p->p)<<PAGE_PRESENT_SHIFT) |
  109.         (1<<PAGE_USER_SHIFT) |
  110.         (1<<PAGE_READ_SHIFT) |
  111.         ((p->w)<<PAGE_WRITE_SHIFT) |
  112.         (1<<PAGE_EXEC_SHIFT) |
  113.         (p->g<<PAGE_GLOBAL_SHIFT)
  114.     );
  115.        
  116. }
  117.  
  118. static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
  119. {
  120.     pte_t *p = &pt[i];
  121.    
  122.     p->cacheable = (flags & PAGE_CACHEABLE) != 0;
  123.     p->p = !(flags & PAGE_NOT_PRESENT);
  124.     p->g = (flags & PAGE_GLOBAL) != 0;
  125.     p->w = (flags & PAGE_WRITE) != 0;
  126.    
  127.     /*
  128.      * Ensure that valid entries have at least one bit set.
  129.      */
  130.     p->soft_valid = 1;
  131. }
  132.  
  133. extern void page_arch_init(void);
  134.  
  135. #endif /* __ASM__ */
  136.  
  137. #endif
  138.