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  1. /*
  2.  * Copyright (C) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #ifndef __ia64_REGISTER_H__
  30. #define __ia64_REGISTER_H__
  31.  
  32. #ifndef __ASM__
  33. #include <arch/types.h>
  34. #endif
  35.  
  36. #define CR_IVR_MASK 0xf
  37. #define PSR_IC_MASK 0x2000
  38. #define PSR_I_MASK  0x4000
  39. #define PSR_PK_MASK 0x8000
  40.  
  41. #define PSR_DT_MASK (1<<17)
  42. #define PSR_RT_MASK (1<<27)
  43. #define PSR_IT_MASK 0x0000001000000000
  44.  
  45.  
  46.  
  47. /** Application registers. */
  48. #define AR_KR0      0
  49. #define AR_KR1      1
  50. #define AR_KR2      2
  51. #define AR_KR3      3
  52. #define AR_KR4      4
  53. #define AR_KR5      5
  54. #define AR_KR6      6
  55. #define AR_KR7      7
  56. /* AR 8-15 reserved */
  57. #define AR_RSC      16
  58. #define AR_BSP      17
  59. #define AR_BSPSTORE 18
  60. #define AR_RNAT     19
  61. /* AR 20 reserved */
  62. #define AR_FCR      21
  63. /* AR 22-23 reserved */
  64. #define AR_EFLAG    24
  65. #define AR_CSD      25
  66. #define AR_SSD      26
  67. #define AR_CFLG     27
  68. #define AR_FSR      28
  69. #define AR_FIR      29
  70. #define AR_FDR      30
  71. /* AR 31 reserved */
  72. #define AR_CCV      32
  73. /* AR 33-35 reserved */
  74. #define AR_UNAT     36
  75. /* AR 37-39 reserved */
  76. #define AR_FPSR     40
  77. /* AR 41-43 reserved */
  78. #define AR_ITC      44
  79. /* AR 45-47 reserved */
  80. /* AR 48-63 ignored */
  81. #define AR_PFS      64
  82. #define AR_LC       65
  83. #define AR_EC       66
  84. /* AR 67-111 reserved */
  85. /* AR 112-127 ignored */
  86.  
  87. /** Control registers. */
  88. #define CR_DCR      0
  89. #define CR_ITM      1
  90. #define CR_IVA      2
  91. /* CR3-CR7 reserved */
  92. #define CR_PTA      8
  93. /* CR9-CR15 reserved */
  94. #define CR_IPSR     16
  95. #define CR_ISR      17
  96. /* CR18 reserved */
  97. #define CR_IIP      19
  98. #define CR_IFA      20
  99. #define CR_ITIR     21
  100. #define CR_IIPA     22
  101. #define CR_IFS      23
  102. #define CR_IIM      24
  103. #define CR_IHA      25
  104. /* CR26-CR63 reserved */
  105. #define CR_LID      64
  106. #define CR_IVR      65
  107. #define CR_TPR      66
  108. #define CR_EOI      67
  109. #define CR_IRR0     68
  110. #define CR_IRR1     69
  111. #define CR_IRR2     70
  112. #define CR_IRR3     71
  113. #define CR_ITV      72
  114. #define CR_PMV      73
  115. #define CR_CMCV     74
  116. /* CR75-CR79 reserved */
  117. #define CR_LRR0     80
  118. #define CR_LRR1     81
  119. /* CR82-CR127 reserved */
  120.  
  121. #ifndef __ASM__
  122. /** External Interrupt Vector Register */
  123. union cr_ivr {
  124.     __u8  vector;
  125.     __u64 value;
  126. };
  127.  
  128. typedef union cr_ivr cr_ivr_t;
  129.  
  130. /** Task Priority Register */
  131. union cr_tpr {
  132.     struct {
  133.         unsigned : 4;
  134.         unsigned mic: 4;        /**< Mask Interrupt Class. */
  135.         unsigned : 8;
  136.         unsigned mmi: 1;        /**< Mask Maskable Interrupts. */
  137.     } __attribute__ ((packed));
  138.     __u64 value;
  139. };
  140.  
  141. typedef union cr_tpr cr_tpr_t;
  142.  
  143. /** Interval Timer Vector */
  144. union cr_itv {
  145.     struct {
  146.         unsigned vector : 8;
  147.         unsigned : 4;
  148.         unsigned : 1;
  149.         unsigned : 3;
  150.         unsigned m : 1;         /**< Mask. */
  151.     } __attribute__ ((packed));
  152.     __u64 value;
  153. };
  154.  
  155. typedef union cr_itv cr_itv_t;
  156.  
  157. /** Interruption Status Register */
  158. union cr_isr {
  159.     struct {
  160.         union {
  161.             /** General Exception code field structuring. */
  162.             struct {
  163.                 unsigned ge_na : 4;
  164.                 unsigned ge_code : 4;
  165.             } __attribute__ ((packed));
  166.             __u16 code;
  167.         };
  168.         __u8 vector;
  169.         unsigned : 8;
  170.         unsigned x : 1;         /**< Execute exception. */
  171.         unsigned w : 1;         /**< Write exception. */
  172.         unsigned r : 1;         /**< Read exception. */
  173.         unsigned na : 1;        /**< Non-access exception. */
  174.         unsigned sp : 1;        /**< Speculative load exception. */
  175.         unsigned rs : 1;        /**< Register stack. */
  176.         unsigned ir : 1;        /**< Incomplete Register frame. */
  177.         unsigned ni : 1;        /**< Nested Interruption. */
  178.         unsigned so : 1;        /**< IA-32 Supervisor Override. */
  179.         unsigned ei : 2;        /**< Excepting Instruction. */
  180.         unsigned ed : 1;        /**< Exception Deferral. */
  181.         unsigned : 20;
  182.     } __attribute__ ((packed));
  183.     __u64 value;
  184. };
  185.  
  186. typedef union cr_isr cr_isr_t;
  187.  
  188. /** CPUID Register 3 */
  189. union cpuid3 {
  190.     struct {
  191.         __u8 number;
  192.         __u8 revision;
  193.         __u8 model;
  194.         __u8 family;
  195.         __u8 archrev;
  196.     } __attribute__ ((packed));
  197.     __u64 value;
  198. };
  199.  
  200. typedef union cpuid3 cpuid3_t;
  201.  
  202. #endif /* !__ASM__ */
  203.  
  204. #endif
  205.