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  1. /*
  2.  * Copyright (C) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #ifndef __ia64_REGISTER_H__
  30. #define __ia64_REGISTER_H__
  31.  
  32. #ifndef __ASM__
  33. #include <arch/types.h>
  34. #endif
  35.  
  36. #define CR_IVR_MASK 0xf
  37. #define PSR_IC_MASK 0x2000
  38. #define PSR_I_MASK  0x4000
  39. #define PSR_PK_MASK 0x8000
  40.  
  41. /** Application registers. */
  42. #define AR_KR0      0
  43. #define AR_KR1      1
  44. #define AR_KR2      2
  45. #define AR_KR3      3
  46. #define AR_KR4      4
  47. #define AR_KR5      5
  48. #define AR_KR6      6
  49. #define AR_KR7      7
  50. /* AR 8-15 reserved */
  51. #define AR_RSC      16
  52. #define AR_BSP      17
  53. #define AR_BSPSTORE 18
  54. #define AR_RNAT     19
  55. /* AR 20 reserved */
  56. #define AR_FCR      21
  57. /* AR 22-23 reserved */
  58. #define AR_EFLAG    24
  59. #define AR_CSD      25
  60. #define AR_SSD      26
  61. #define AR_CFLG     27
  62. #define AR_FSR      28
  63. #define AR_FIR      29
  64. #define AR_FDR      30
  65. /* AR 31 reserved */
  66. #define AR_CCV      32
  67. /* AR 33-35 reserved */
  68. #define AR_UNAT     36
  69. /* AR 37-39 reserved */
  70. #define AR_FPSR     40
  71. /* AR 41-43 reserved */
  72. #define AR_ITC      44
  73. /* AR 45-47 reserved */
  74. /* AR 48-63 ignored */
  75. #define AR_PFS      64
  76. #define AR_LC       65
  77. #define AR_EC       66
  78. /* AR 67-111 reserved */
  79. /* AR 112-127 ignored */
  80.  
  81. /** Control registers. */
  82. #define CR_DCR      0
  83. #define CR_ITM      1
  84. #define CR_IVA      2
  85. /* CR3-CR7 reserved */
  86. #define CR_PTA      8
  87. /* CR9-CR15 reserved */
  88. #define CR_IPSR     16
  89. #define CR_ISR      17
  90. /* CR18 reserved */
  91. #define CR_IIP      19
  92. #define CR_IFA      20
  93. #define CR_ITIR     21
  94. #define CR_IIPA     22
  95. #define CR_IFS      23
  96. #define CR_IIM      24
  97. #define CR_IHA      25
  98. /* CR26-CR63 reserved */
  99. #define CR_LID      64
  100. #define CR_IVR      65
  101. #define CR_TPR      66
  102. #define CR_EOI      67
  103. #define CR_IRR0     68
  104. #define CR_IRR1     69
  105. #define CR_IRR2     70
  106. #define CR_IRR3     71
  107. #define CR_ITV      72
  108. #define CR_PMV      73
  109. #define CR_CMCV     74
  110. /* CR75-CR79 reserved */
  111. #define CR_LRR0     80
  112. #define CR_LRR1     81
  113. /* CR82-CR127 reserved */
  114.  
  115. #ifndef __ASM__
  116. /** External Interrupt Vector Register */
  117. union cr_ivr {
  118.     __u8  vector;
  119.     __u64 value;
  120. };
  121.  
  122. typedef union cr_ivr cr_ivr_t;
  123.  
  124. /** Task Priority Register */
  125. union cr_tpr {
  126.     struct {
  127.         unsigned : 4;
  128.         unsigned mic: 4;        /**< Mask Interrupt Class. */
  129.         unsigned : 8;
  130.         unsigned mmi: 1;        /**< Mask Maskable Interrupts. */
  131.     } __attribute__ ((packed));
  132.     __u64 value;
  133. };
  134.  
  135. typedef union cr_tpr cr_tpr_t;
  136.  
  137. /** Interval Timer Vector */
  138. union cr_itv {
  139.     struct {
  140.         unsigned vector : 8;
  141.         unsigned : 4;
  142.         unsigned : 1;
  143.         unsigned : 3;
  144.         unsigned m : 1;         /**< Mask. */
  145.     } __attribute__ ((packed));
  146.     __u64 value;
  147. };
  148.  
  149. typedef union cr_itv cr_itv_t;
  150.  
  151. /** Interruption Status Register */
  152. union cr_isr {
  153.     struct {
  154.         union {
  155.             /** General Exception code field structuring. */
  156.             struct {
  157.                 unsigned ge_na : 4;
  158.                 unsigned ge_code : 4;
  159.             } __attribute__ ((packed));
  160.             __u16 code;
  161.         };
  162.         __u8 vector;
  163.         unsigned : 8;
  164.         unsigned x : 1;         /**< Execute exception. */
  165.         unsigned w : 1;         /**< Write exception. */
  166.         unsigned r : 1;         /**< Read exception. */
  167.         unsigned na : 1;        /**< Non-access exception. */
  168.         unsigned sp : 1;        /**< Speculative load exception. */
  169.         unsigned rs : 1;        /**< Register stack. */
  170.         unsigned ir : 1;        /**< Incomplete Register frame. */
  171.         unsigned ni : 1;        /**< Nested Interruption. */
  172.         unsigned so : 1;        /**< IA-32 Supervisor Override. */
  173.         unsigned ei : 2;        /**< Excepting Instruction. */
  174.         unsigned ed : 1;        /**< Exception Deferral. */
  175.         unsigned : 20;
  176.     } __attribute__ ((packed));
  177.     __u64 value;
  178. };
  179.  
  180. typedef union cr_isr cr_isr_t;
  181.  
  182. /** CPUID Register 3 */
  183. union cpuid3 {
  184.     struct {
  185.         __u8 number;
  186.         __u8 revision;
  187.         __u8 model;
  188.         __u8 family;
  189.         __u8 archrev;
  190.     } __attribute__ ((packed));
  191.     __u64 value;
  192. };
  193.  
  194. typedef union cpuid3 cpuid3_t;
  195.  
  196. #endif /* !__ASM__ */
  197.  
  198. #endif
  199.