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  1. /*
  2.  * Copyright (C) 2001-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #include <arch/types.h>
  30. #include <arch/smp/apic.h>
  31. #include <arch/smp/ap.h>
  32. #include <arch/smp/mps.h>
  33. #include <mm/page.h>
  34. #include <time/delay.h>
  35. #include <arch/interrupt.h>
  36. #include <print.h>
  37. #include <arch/asm.h>
  38. #include <arch.h>
  39.  
  40. #ifdef __SMP__
  41.  
  42. /*
  43.  * This is functional, far-from-general-enough interface to the APIC.
  44.  * Advanced Programmable Interrupt Controller for MP systems.
  45.  * Tested on:
  46.  *  Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs
  47.  *  Simics 2.0.28 - Simics 2.2.14 2-4 CPUs
  48.  *  ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
  49.  */
  50.  
  51. /*
  52.  * These variables either stay configured as initilalized, or are changed by
  53.  * the MP configuration code.
  54.  *
  55.  * Pay special attention to the volatile keyword. Without it, gcc -O2 would
  56.  * optimize the code too much and accesses to l_apic and io_apic, that must
  57.  * always be 32-bit, would use byte oriented instructions.
  58.  */
  59. volatile __u32 *l_apic = (__u32 *) 0xfee00000;
  60. volatile __u32 *io_apic = (__u32 *) 0xfec00000;
  61.  
  62. __u32 apic_id_mask = 0;
  63.  
  64. int apic_poll_errors(void);
  65.  
  66. void apic_init(void)
  67. {
  68.     __u32 tmp, id, i;
  69.  
  70.     trap_register(VECTOR_APIC_SPUR, apic_spurious);
  71.  
  72.     enable_irqs_function = io_apic_enable_irqs;
  73.     disable_irqs_function = io_apic_disable_irqs;
  74.     eoi_function = l_apic_eoi;
  75.    
  76.     /*
  77.      * Configure interrupt routing.
  78.      * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
  79.      * Other interrupts will be forwarded to the lowest priority CPU.
  80.      */
  81.     io_apic_disable_irqs(0xffff);
  82.     trap_register(VECTOR_CLK, l_apic_timer_interrupt);
  83.     for (i=1; i<16; i++) {
  84.         int pin;
  85.    
  86.         if ((pin = mps_irq_to_pin(i)) != -1)
  87.         io_apic_change_ioredtbl(pin,0xf,IVT_IRQBASE+i,LOPRI);
  88.     }
  89.    
  90.  
  91.     /*
  92.      * Ensure that io_apic has unique ID.
  93.      */
  94.     tmp = io_apic_read(IOAPICID);
  95.     id = (tmp >> 24) & 0xf;
  96.     if ((1<<id) & apic_id_mask) {
  97.         int i;
  98.        
  99.         for (i=0; i<15; i++) {
  100.             if (!((1<<i) & apic_id_mask)) {
  101.                 io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) | (i<<24));
  102.                 break;
  103.             }
  104.         }
  105.     }
  106.  
  107.     /*
  108.      * Configure the BSP's lapic.
  109.      */
  110.     l_apic_init();
  111.     l_apic_debug();
  112. }
  113.  
  114. void apic_spurious(__u8 n, __u32 stack[])
  115. {
  116.     printf("cpu%d: APIC spurious interrupt\n", CPU->id);
  117. }
  118.  
  119. int apic_poll_errors(void)
  120. {
  121.     __u32 esr;
  122.    
  123.     esr = l_apic[ESR] & ~ESRClear;
  124.    
  125.     if ((esr>>0) & 1)
  126.         printf("Send CS Error\n");
  127.     if ((esr>>1) & 1)
  128.         printf("Receive CS Error\n");
  129.     if ((esr>>2) & 1)
  130.         printf("Send Accept Error\n");
  131.     if ((esr>>3) & 1)
  132.         printf("Receive Accept Error\n");
  133.     if ((esr>>5) & 1)
  134.         printf("Send Illegal Vector\n");
  135.     if ((esr>>6) & 1)
  136.         printf("Received Illegal Vector\n");
  137.     if ((esr>>7) & 1)
  138.         printf("Illegal Register Address\n");
  139.  
  140.     return !esr;
  141. }
  142.  
  143. /*
  144.  * Send all CPUs excluding CPU IPI vector.
  145.  */
  146. int l_apic_broadcast_custom_ipi(__u8 vector)
  147. {
  148.     __u32 lo;
  149.  
  150.     /*
  151.      * Read the ICR register in and zero all non-reserved fields.
  152.      */
  153.     lo = l_apic[ICRlo] & ICRloClear;
  154.  
  155.     lo |= DLVRMODE_FIXED | DESTMODE_LOGIC | LEVEL_ASSERT | SHORTHAND_EXCL | TRGRMODE_LEVEL | vector;
  156.    
  157.     l_apic[ICRlo] = lo;
  158.  
  159.     lo = l_apic[ICRlo] & ICRloClear;
  160.     if (lo & SEND_PENDING)
  161.         printf("IPI is pending.\n");
  162.  
  163.     return apic_poll_errors();
  164. }
  165.  
  166. /*
  167.  * Universal Start-up Algorithm for bringing up the AP processors.
  168.  */
  169. int l_apic_send_init_ipi(__u8 apicid)
  170. {
  171.     __u32 lo, hi;
  172.     int i;
  173.  
  174.     /*
  175.      * Read the ICR register in and zero all non-reserved fields.
  176.      */
  177.     lo = l_apic[ICRlo] & ICRloClear;
  178.     hi = l_apic[ICRhi] & ICRhiClear;
  179.    
  180.     lo |= DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
  181.     hi |= apicid << 24;
  182.    
  183.     l_apic[ICRhi] = hi;
  184.     l_apic[ICRlo] = lo;
  185.  
  186.     /*
  187.      * According to MP Specification, 20us should be enough to
  188.      * deliver the IPI.
  189.      */
  190.     delay(20);
  191.  
  192.     if (!apic_poll_errors()) return 0;
  193.  
  194.     lo = l_apic[ICRlo] & ICRloClear;
  195.     if (lo & SEND_PENDING)
  196.         printf("IPI is pending.\n");
  197.  
  198.     l_apic[ICRlo] = lo | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
  199.  
  200.     /*
  201.      * Wait 10ms as MP Specification specifies.
  202.      */
  203.     delay(10000);
  204.  
  205.     if (!is_82489DX_apic(l_apic[LAVR])) {
  206.         /*
  207.          * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
  208.          */
  209.         for (i = 0; i<2; i++) {
  210.             lo = l_apic[ICRlo] & ICRloClear;
  211.             lo |= ((__address) ap_boot) / 4096; /* calculate the reset vector */
  212.             l_apic[ICRlo] = lo | DLVRMODE_STUP | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
  213.             delay(200);
  214.         }
  215.     }
  216.    
  217.    
  218.     return apic_poll_errors();
  219. }
  220.  
  221. void l_apic_init(void)
  222. {
  223.     __u32 tmp, t1, t2;
  224.  
  225.     l_apic[LVT_Err] |= (1<<16);
  226.     l_apic[LVT_LINT0] |= (1<<16);
  227.     l_apic[LVT_LINT1] |= (1<<16);
  228.  
  229.     tmp = l_apic[SVR] & SVRClear;
  230.     l_apic[SVR] = tmp | (1<<8) | (VECTOR_APIC_SPUR);
  231.  
  232.     l_apic[TPR] &= TPRClear;
  233.  
  234.     if (CPU->arch.family >= 6)
  235.         enable_l_apic_in_msr();
  236.    
  237.     tmp = l_apic[ICRlo] & ICRloClear;
  238.     l_apic[ICRlo] = tmp | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_INCL | TRGRMODE_LEVEL;
  239.    
  240.     /*
  241.      * Program the timer for periodic mode and respective vector.
  242.      */
  243.  
  244.     l_apic[TDCR] &= TDCRClear;
  245.     l_apic[TDCR] |= 0xb;
  246.     tmp = l_apic[LVT_Tm] | (1<<17) | (VECTOR_CLK);
  247.     l_apic[LVT_Tm] = tmp & ~(1<<16);
  248.  
  249.     t1 = l_apic[CCRT];
  250.     l_apic[ICRT] = 0xffffffff;
  251.  
  252.     while (l_apic[CCRT] == t1)
  253.         ;
  254.        
  255.     t1 = l_apic[CCRT];
  256.     delay(1000);
  257.     t2 = l_apic[CCRT];
  258.    
  259.     l_apic[ICRT] = t1-t2;
  260.    
  261. }
  262.  
  263. void l_apic_eoi(void)
  264. {
  265.     l_apic[EOI] = 0;
  266. }
  267.  
  268. void l_apic_debug(void)
  269. {
  270. #ifdef LAPIC_VERBOSE
  271.     int i, lint;
  272.  
  273.     printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
  274.  
  275.     printf("LVT_Tm: ");
  276.     if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(',');   
  277.     if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
  278.     if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
  279.     printf("%B\n", l_apic[LVT_Tm] & 0xff);
  280.    
  281.     for (i=0; i<2; i++) {
  282.         lint = i ? LVT_LINT1 : LVT_LINT0;
  283.         printf("LVT_LINT%d: ", i);
  284.         if (l_apic[lint] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
  285.         if (l_apic[lint] & (1<<15)) printf("level"); else printf("edge"); putchar(',');
  286.         printf("%d", l_apic[lint] & (1<<14)); putchar(',');
  287.         printf("%d", l_apic[lint] & (1<<13)); putchar(',');
  288.         if (l_apic[lint] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
  289.    
  290.         switch ((l_apic[lint]>>8)&7) {
  291.             case 0: printf("fixed"); break;
  292.             case 4: printf("NMI"); break;
  293.             case 7: printf("ExtINT"); break;
  294.         }
  295.         putchar(',');
  296.         printf("%B\n", l_apic[lint] & 0xff);   
  297.     }
  298.  
  299.     printf("LVT_Err: ");
  300.     if (l_apic[LVT_Err] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
  301.     if (l_apic[LVT_Err] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
  302.     printf("%B\n", l_apic[LVT_Err] & 0xff);
  303.  
  304.     /*
  305.      * This register is supported only on P6 and higher.
  306.      */
  307.     if (CPU->arch.family > 5) {
  308.         printf("LVT_PCINT: ");
  309.         if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
  310.         if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
  311.         switch ((l_apic[LVT_PCINT] >> 8)&7) {
  312.             case 0: printf("fixed"); break;
  313.             case 4: printf("NMI"); break;
  314.             case 7: printf("ExtINT"); break;
  315.         }
  316.         putchar(',');
  317.         printf("%B\n", l_apic[LVT_PCINT] & 0xff);
  318.     }
  319. #endif
  320. }
  321.  
  322. void l_apic_timer_interrupt(__u8 n, __u32 stack[])
  323. {
  324.     l_apic_eoi();
  325.     clock();
  326. }
  327.  
  328. __u8 l_apic_id(void)
  329. {
  330.     return (l_apic[L_APIC_ID] >> L_APIC_IDShift)&L_APIC_IDMask;
  331. }
  332.  
  333. __u32 io_apic_read(__u8 address)
  334. {
  335.     __u32 tmp;
  336.    
  337.     tmp = io_apic[IOREGSEL] & ~0xf;
  338.     io_apic[IOREGSEL] = tmp | address;
  339.     return io_apic[IOWIN];
  340. }
  341.  
  342. void io_apic_write(__u8 address, __u32 x)
  343. {
  344.     __u32 tmp;
  345.  
  346.     tmp = io_apic[IOREGSEL] & ~0xf;
  347.     io_apic[IOREGSEL] = tmp | address;
  348.     io_apic[IOWIN] = x;
  349. }
  350.  
  351. void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags)
  352. {
  353.     __u32 reglo, reghi;
  354.     int dlvr = 0;
  355.    
  356.     if (flags & LOPRI)
  357.         dlvr = 1;
  358.    
  359.     reglo = io_apic_read(IOREDTBL + signal*2);
  360.     reghi = io_apic_read(IOREDTBL + signal*2 + 1);
  361.    
  362.     reghi &= ~0x0f000000;
  363.     reghi |= (dest<<24);
  364.  
  365.     reglo &= (~0x1ffff) | (1<<16); /* don't touch the mask */
  366.     reglo |= (0<<15) | (0<<13) | (0<<11) | (dlvr<<8) | v;
  367.  
  368.     io_apic_write(IOREDTBL + signal*2, reglo);     
  369.     io_apic_write(IOREDTBL + signal*2 + 1, reghi);
  370. }
  371.  
  372. void io_apic_disable_irqs(__u16 irqmask)
  373. {
  374.     int i,pin;
  375.     __u32 reglo;
  376.    
  377.     for (i=0;i<16;i++) {
  378.         if ((irqmask>>i) & 1) {
  379.             /*
  380.              * Mask the signal input in IO APIC if there is a
  381.              * mapping for the respective IRQ number.
  382.              */
  383.             pin = mps_irq_to_pin(i);
  384.             if (pin != -1) {
  385.                 reglo = io_apic_read(IOREDTBL + pin*2);
  386.                 reglo |= (1<<16);
  387.                 io_apic_write(IOREDTBL + pin*2,reglo);
  388.             }
  389.            
  390.         }
  391.     }
  392. }
  393.  
  394. void io_apic_enable_irqs(__u16 irqmask)
  395. {
  396.     int i,pin;
  397.     __u32 reglo;
  398.    
  399.     for (i=0;i<16;i++) {
  400.         if ((irqmask>>i) & 1) {
  401.             /*
  402.              * Unmask the signal input in IO APIC if there is a
  403.              * mapping for the respective IRQ number.
  404.              */
  405.             pin = mps_irq_to_pin(i);
  406.             if (pin != -1) {
  407.                 reglo = io_apic_read(IOREDTBL + pin*2);
  408.                 reglo &= ~(1<<16);
  409.                 io_apic_write(IOREDTBL + pin*2,reglo);
  410.             }
  411.            
  412.         }
  413.     }
  414.  
  415. }
  416.  
  417. #endif /* __SMP__ */
  418.