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  1. /*
  2.  * Copyright (C) 2001-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #include <arch/pm.h>
  30. #include <config.h>
  31. #include <arch/types.h>
  32. #include <typedefs.h>
  33. #include <arch/interrupt.h>
  34. #include <arch/asm.h>
  35. #include <arch/context.h>
  36. #include <panic.h>
  37. #include <arch/mm/page.h>
  38. #include <mm/slab.h>
  39. #include <memstr.h>
  40. #include <arch/boot/boot.h>
  41. #include <interrupt.h>
  42.  
  43. /*
  44.  * Early ia32 configuration functions and data structures.
  45.  */
  46.  
  47. /*
  48.  * We have no use for segmentation so we set up flat mode. In this
  49.  * mode, we use, for each privilege level, two segments spanning the
  50.  * whole memory. One is for code and one is for data.
  51.  */
  52. struct descriptor gdt[GDT_ITEMS] = {
  53.     /* NULL descriptor */
  54.     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
  55.     /* KTEXT descriptor */
  56.     { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
  57.     /* KDATA descriptor */
  58.     { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
  59.     /* UTEXT descriptor */
  60.     { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
  61.     /* UDATA descriptor */
  62.     { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
  63.     /* TSS descriptor - set up will be completed later */
  64.     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
  65. };
  66.  
  67. static struct idescriptor idt[IDT_ITEMS];
  68.  
  69. static struct tss tss;
  70.  
  71. struct tss *tss_p = NULL;
  72.  
  73. /* gdtr is changed by kmp before next CPU is initialized */
  74. struct ptr_16_32 bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((__address) gdt) };
  75. struct ptr_16_32 gdtr = { .limit = sizeof(gdt), .base = (__address) gdt };
  76.  
  77. void gdt_setbase(struct descriptor *d, __address base)
  78. {
  79.     d->base_0_15 = base & 0xffff;
  80.     d->base_16_23 = ((base) >> 16) & 0xff;
  81.     d->base_24_31 = ((base) >> 24) & 0xff;
  82. }
  83.  
  84. void gdt_setlimit(struct descriptor *d, __u32 limit)
  85. {
  86.     d->limit_0_15 = limit & 0xffff;
  87.     d->limit_16_19 = (limit >> 16) & 0xf;
  88. }
  89.  
  90. void idt_setoffset(struct idescriptor *d, __address offset)
  91. {
  92.     /*
  93.      * Offset is a linear address.
  94.      */
  95.     d->offset_0_15 = offset & 0xffff;
  96.     d->offset_16_31 = offset >> 16;
  97. }
  98.  
  99. void tss_initialize(struct tss *t)
  100. {
  101.     memsetb((__address) t, sizeof(struct tss), 0);
  102. }
  103.  
  104. /*
  105.  * This function takes care of proper setup of IDT and IDTR.
  106.  */
  107. void idt_init(void)
  108. {
  109.     struct idescriptor *d;
  110.     int i;
  111.  
  112.     for (i = 0; i < IDT_ITEMS; i++) {
  113.         d = &idt[i];
  114.  
  115.         d->unused = 0;
  116.         d->selector = selector(KTEXT_DES);
  117.  
  118.         d->access = AR_PRESENT | AR_INTERRUPT;  /* masking interrupt */
  119.  
  120.         if (i == VECTOR_SYSCALL) {
  121.             /*
  122.              * The syscall interrupt gate must be calleable from userland.
  123.              */
  124.             d->access |= DPL_USER;
  125.         }
  126.        
  127.         idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
  128.         exc_register(i, "undef", null_interrupt);
  129.     }
  130.     exc_register(13, "gp_fault", gp_fault);
  131.     exc_register( 7, "nm_fault", nm_fault);
  132.     exc_register(12, "ss_fault", ss_fault);
  133. }
  134.  
  135.  
  136. /* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
  137. static void clean_IOPL_NT_flags(void)
  138. {
  139.     asm
  140.     (
  141.         "pushfl;"
  142.         "pop %%eax;"
  143.         "and $0xffff8fff,%%eax;"
  144.         "push %%eax;"
  145.         "popfl;"
  146.         :
  147.         :
  148.         :"%eax"
  149.     );
  150. }
  151.  
  152. /* Clean AM(18) flag in CR0 register */
  153. static void clean_AM_flag(void)
  154. {
  155.     asm
  156.     (
  157.         "mov %%cr0,%%eax;"
  158.         "and $0xFFFBFFFF,%%eax;"
  159.         "mov %%eax,%%cr0;"
  160.         :
  161.         :
  162.         :"%eax"
  163.     );
  164. }
  165.  
  166. void pm_init(void)
  167. {
  168.     struct descriptor *gdt_p = (struct descriptor *) gdtr.base;
  169.     struct ptr_16_32 idtr;
  170.  
  171.     /*
  172.      * Update addresses in GDT and IDT to their virtual counterparts.
  173.      */
  174.     idtr.limit = sizeof(idt);
  175.     idtr.base = (__address) idt;
  176.     __asm__ volatile ("lgdt %0\n" : : "m" (gdtr));
  177.     __asm__ volatile ("lidt %0\n" : : "m" (idtr)); 
  178.    
  179.     /*
  180.      * Each CPU has its private GDT and TSS.
  181.      * All CPUs share one IDT.
  182.      */
  183.  
  184.     if (config.cpu_active == 1) {
  185.         idt_init();
  186.         /*
  187.          * NOTE: bootstrap CPU has statically allocated TSS, because
  188.          * the heap hasn't been initialized so far.
  189.          */
  190.         tss_p = &tss;
  191.     }
  192.     else {
  193.         tss_p = (struct tss *) malloc(sizeof(struct tss));
  194.         if (!tss_p)
  195.             panic("could not allocate TSS\n");
  196.     }
  197.  
  198.     tss_initialize(tss_p);
  199.    
  200.     gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
  201.     gdt_p[TSS_DES].special = 1;
  202.     gdt_p[TSS_DES].granularity = 1;
  203.    
  204.     gdt_setbase(&gdt_p[TSS_DES], (__address) tss_p);
  205.     gdt_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1);
  206.  
  207.     /*
  208.      * As of this moment, the current CPU has its own GDT pointing
  209.      * to its own TSS. We just need to load the TR register.
  210.      */
  211.     __asm__ volatile ("ltr %0" : : "r" ((__u16) selector(TSS_DES)));
  212.    
  213.     clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels */
  214.     clean_AM_flag();          /* Disable alignment check */
  215. }
  216.