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  1. /*
  2.  * Copyright (C) 2001-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #ifndef __APIC_H__
  30. #define __APIC_H__
  31.  
  32. #include <arch/types.h>
  33. #include <cpu.h>
  34.  
  35. #define FIXED       (0<<0)
  36. #define LOPRI       (1<<0)
  37.  
  38. /* local APIC macros */
  39. #define IPI_INIT    0
  40. #define IPI_STARTUP 0
  41.  
  42. /** Delivery modes. */
  43. #define DELMOD_FIXED    0x0
  44. #define DELMOD_LOWPRI   0x1
  45. #define DELMOD_SMI  0x2
  46. /* 0x3 reserved */
  47. #define DELMOD_NMI  0x4
  48. #define DELMOD_INIT 0x5
  49. #define DELMOD_STARTUP  0x6
  50. #define DELMOD_EXTINT   0x7
  51.  
  52. /** Destination modes. */
  53. #define DESTMOD_PHYS    0x0
  54. #define DESTMOD_LOGIC   0x1
  55.  
  56. /** Trigger Modes. */
  57. #define TRIGMOD_EDGE    0x0
  58. #define TRIGMOD_LEVEL   0x1
  59.  
  60. /** Levels. */
  61. #define LEVEL_DEASSERT  0x0
  62. #define LEVEL_ASSERT    0x1
  63.  
  64. /** Destination Shorthands. */
  65. #define SHORTHAND_NONE      0x0
  66. #define SHORTHAND_SELF      0x1
  67. #define SHORTHAND_ALL_INCL  0x2
  68. #define SHORTHAND_ALL_EXCL  0x3
  69.  
  70. /** Interrupt Input Pin Polarities. */
  71. #define POLARITY_HIGH   0x0
  72. #define POLARITY_LOW    0x1
  73.  
  74. /** Divide Values. (Bit 2 is always 0) */
  75. #define DIVIDE_2    0x0
  76. #define DIVIDE_4    0x1
  77. #define DIVIDE_8    0x2
  78. #define DIVIDE_16   0x3
  79. #define DIVIDE_32   0x8
  80. #define DIVIDE_64   0x9
  81. #define DIVIDE_128  0xa
  82. #define DIVIDE_1    0xb
  83.  
  84. /** Timer Modes. */
  85. #define TIMER_ONESHOT   0x0
  86. #define TIMER_PERIODIC  0x1
  87.  
  88. #define SEND_PENDING    (1<<12)
  89.  
  90. /** Interrupt Command Register. */
  91. #define ICRlo       (0x300/sizeof(__u32))
  92. #define ICRhi       (0x310/sizeof(__u32))
  93. struct icr {
  94.     union {
  95.         __u32 lo;
  96.         struct {
  97.             __u8 vector;            /**< Interrupt Vector. */
  98.             unsigned delmod : 3;        /**< Delivery Mode. */
  99.             unsigned destmod : 1;       /**< Destination Mode. */
  100.             unsigned delivs : 1;        /**< Delivery status (RO). */
  101.             unsigned : 1;           /**< Reserved. */
  102.             unsigned level : 1;     /**< Level. */
  103.             unsigned trigger_mode : 1;  /**< Trigger Mode. */
  104.             unsigned : 2;           /**< Reserved. */
  105.             unsigned shorthand : 2;     /**< Destination Shorthand. */
  106.             unsigned : 12;          /**< Reserved. */
  107.         } __attribute__ ((packed));
  108.     };
  109.     union {
  110.         __u32 hi;
  111.         struct {
  112.             unsigned : 24;          /**< Reserved. */
  113.             __u8 dest;          /**< Destination field. */
  114.         } __attribute__ ((packed));
  115.     };
  116. } __attribute__ ((packed));
  117. typedef struct icr icr_t;
  118.  
  119. /* End Of Interrupt */
  120. #define EOI     (0x0b0/sizeof(__u32))
  121.  
  122. /** Error Status Register. */
  123. #define ESR     (0x280/sizeof(__u32))
  124. union esr {
  125.     __u32 value;
  126.     __u8 err_bitmap;
  127.     struct {
  128.         unsigned send_checksum_error : 1;
  129.         unsigned receive_checksum_error : 1;
  130.         unsigned send_accept_error : 1;
  131.         unsigned receive_accept_error : 1;
  132.         unsigned : 1;
  133.         unsigned send_illegal_vector : 1;
  134.         unsigned received_illegal_vector : 1;
  135.         unsigned illegal_register_address : 1;
  136.         unsigned : 24;
  137.     } __attribute__ ((packed));
  138. };
  139. typedef union esr esr_t;
  140.  
  141. /* Task Priority Register */
  142. #define TPR     (0x080/sizeof(__u32))
  143. #define TPRClear    0xffffff00
  144.  
  145. /** Spurious-Interrupt Vector Register. */
  146. #define SVR     (0x0f0/sizeof(__u32))
  147. union svr {
  148.     __u32 value;
  149.     struct {
  150.         __u8 vector;            /**< Spurious Vector */
  151.         unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable */
  152.         unsigned focus_checking : 1;    /**< Focus Processor Checking */
  153.         unsigned : 22;          /**< Reserved. */
  154.     } __attribute__ ((packed));
  155. };
  156. typedef union svr svr_t;
  157.  
  158. /** Time Divide Configuration Register. */
  159. #define TDCR        (0x3e0/sizeof(__u32))
  160. union tdcr {
  161.     __u32 value;
  162.     struct {
  163.         unsigned div_value : 4;     /**< Divide Value, bit 2 is always 0. */
  164.         unsigned : 28;          /**< Reserved. */
  165.     } __attribute__ ((packed));
  166. };
  167. typedef union tdcr tdcr_t;
  168.  
  169. /* Initial Count Register for Timer */
  170. #define ICRT        (0x380/sizeof(__u32))
  171.  
  172. /* Current Count Register for Timer */
  173. #define CCRT        (0x390/sizeof(__u32))
  174.  
  175. /** LVT Timer register. */
  176. #define LVT_Tm      (0x320/sizeof(__u32))
  177. union lvt_tm {
  178.     __u32 value;
  179.     struct {
  180.         __u8 vector;        /**< Local Timer Interrupt vector. */
  181.         unsigned : 4;       /**< Reserved. */
  182.         unsigned delivs : 1;    /**< Delivery status (RO). */
  183.         unsigned : 3;       /**< Reserved. */
  184.         unsigned masked : 1;    /**< Interrupt Mask. */
  185.         unsigned mode : 1;  /**< Timer Mode. */
  186.         unsigned : 14;      /**< Reserved. */
  187.     } __attribute__ ((packed));
  188. };
  189. typedef union lvt_tm lvt_tm_t;
  190.  
  191. /** LVT LINT registers. */
  192. #define LVT_LINT0   (0x350/sizeof(__u32))
  193. #define LVT_LINT1   (0x360/sizeof(__u32))
  194. union lvt_lint {
  195.     __u32 value;
  196.     struct {
  197.         __u8 vector;            /**< LINT Interrupt vector. */
  198.         unsigned delmod : 3;        /**< Delivery Mode. */
  199.         unsigned : 1;           /**< Reserved. */
  200.         unsigned delivs : 1;        /**< Delivery status (RO). */
  201.         unsigned intpol : 1;        /**< Interrupt Input Pin Polarity. */
  202.         unsigned irr : 1;       /**< Remote IRR (RO). */
  203.         unsigned trigger_mode : 1;  /**< Trigger Mode. */
  204.         unsigned masked : 1;        /**< Interrupt Mask. */
  205.         unsigned : 15;          /**< Reserved. */
  206.     } __attribute__ ((packed));
  207. };
  208. typedef union lvt_lint lvt_lint_t;
  209.  
  210. /** LVT Error register. */
  211. #define LVT_Err     (0x370/sizeof(__u32))
  212. union lvt_error {
  213.     __u32 value;
  214.     struct {
  215.         __u8 vector;        /**< Local Timer Interrupt vector. */
  216.         unsigned : 4;       /**< Reserved. */
  217.         unsigned delivs : 1;    /**< Delivery status (RO). */
  218.         unsigned : 3;       /**< Reserved. */
  219.         unsigned masked : 1;    /**< Interrupt Mask. */
  220.         unsigned : 15;      /**< Reserved. */
  221.     } __attribute__ ((packed));
  222. };
  223. typedef union lvt_error lvt_error_t;
  224.  
  225. /** Local APIC ID Register. */
  226. #define L_APIC_ID   (0x020/sizeof(__u32))
  227. union lapic_id {
  228.     __u32 value;
  229.     struct {
  230.         unsigned : 24;      /**< Reserved. */
  231.         __u8 apic_id;       /**< Local APIC ID. */
  232.     } __attribute__ ((packed));
  233. };
  234. typedef union lapic_id lapic_id_t;
  235.  
  236. /* Local APIC Version Register */
  237. #define LAVR        (0x030/sizeof(__u32))
  238. #define LAVR_Mask   0xff
  239. #define is_local_apic(x)    (((x)&LAVR_Mask&0xf0)==0x1)
  240. #define is_82489DX_apic(x)  ((((x)&LAVR_Mask&0xf0)==0x0))
  241. #define is_local_xapic(x)   (((x)&LAVR_Mask)==0x14)
  242.  
  243. /* IO APIC */
  244. #define IOREGSEL    (0x00/sizeof(__u32))
  245. #define IOWIN       (0x10/sizeof(__u32))
  246.  
  247. #define IOAPICID    0x00
  248. #define IOAPICVER   0x01
  249. #define IOAPICARB   0x02
  250. #define IOREDTBL    0x10
  251.  
  252. /** I/O Register Select Register. */
  253. union io_regsel {
  254.     __u32 value;
  255.     struct {
  256.         __u8 reg_addr;      /**< APIC Register Address. */
  257.         unsigned : 24;      /**< Reserved. */
  258.     } __attribute__ ((packed));
  259. };
  260. typedef union io_regsel io_regsel_t;
  261.  
  262. /** I/O Redirection Register. */
  263. struct io_redirection_reg {
  264.     union {
  265.         __u32 lo;
  266.         struct {
  267.             __u8 intvec;            /**< Interrupt Vector. */
  268.             unsigned delmod : 3;        /**< Delivery Mode. */
  269.             unsigned destmod : 1;       /**< Destination mode. */
  270.             unsigned delivs : 1;        /**< Delivery status (RO). */
  271.             unsigned intpol : 1;        /**< Interrupt Input Pin Polarity. */
  272.             unsigned irr : 1;       /**< Remote IRR (RO). */
  273.             unsigned trigger_mode : 1;  /**< Trigger Mode. */
  274.             unsigned masked : 1;        /**< Interrupt Mask. */
  275.             unsigned : 15;          /**< Reserved. */
  276.         } __attribute__ ((packed));
  277.     };
  278.     union {
  279.         __u32 hi;
  280.         struct {
  281.             unsigned : 24;          /**< Reserved. */
  282.             __u8 dest : 8;      /**< Destination Field. */
  283.         } __attribute__ ((packed));
  284.     };
  285.    
  286. } __attribute__ ((packed));
  287.  
  288. typedef struct io_redirection_reg io_redirection_reg_t;
  289.  
  290. extern volatile __u32 *l_apic;
  291. extern volatile __u32 *io_apic;
  292.  
  293. extern __u32 apic_id_mask;
  294.  
  295. extern void apic_init(void);
  296. extern void apic_spurious(__u8 n, __native stack[]);
  297.  
  298. extern void l_apic_init(void);
  299. extern void l_apic_eoi(void);
  300. extern int l_apic_broadcast_custom_ipi(__u8 vector);
  301. extern int l_apic_send_init_ipi(__u8 apicid);
  302. extern void l_apic_debug(void);
  303. extern void l_apic_timer_interrupt(__u8 n, __native stack[]);
  304. extern __u8 l_apic_id(void);
  305.  
  306. extern __u32 io_apic_read(__u8 address);
  307. extern void io_apic_write(__u8 address , __u32 x);
  308. extern void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags);
  309. extern void io_apic_disable_irqs(__u16 irqmask);
  310. extern void io_apic_enable_irqs(__u16 irqmask);
  311.  
  312. #endif
  313.