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  1. /*
  2.  * Copyright (C) 2001-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #ifndef __APIC_H__
  30. #define __APIC_H__
  31.  
  32. #include <arch/types.h>
  33. #include <cpu.h>
  34.  
  35. #define FIXED       (0<<0)
  36. #define LOPRI       (1<<0)
  37.  
  38. #define APIC_ID_COUNT   16
  39.  
  40. /* local APIC macros */
  41. #define IPI_INIT    0
  42. #define IPI_STARTUP 0
  43.  
  44. /** Delivery modes. */
  45. #define DELMOD_FIXED    0x0
  46. #define DELMOD_LOWPRI   0x1
  47. #define DELMOD_SMI  0x2
  48. /* 0x3 reserved */
  49. #define DELMOD_NMI  0x4
  50. #define DELMOD_INIT 0x5
  51. #define DELMOD_STARTUP  0x6
  52. #define DELMOD_EXTINT   0x7
  53.  
  54. /** Destination modes. */
  55. #define DESTMOD_PHYS    0x0
  56. #define DESTMOD_LOGIC   0x1
  57.  
  58. /** Trigger Modes. */
  59. #define TRIGMOD_EDGE    0x0
  60. #define TRIGMOD_LEVEL   0x1
  61.  
  62. /** Levels. */
  63. #define LEVEL_DEASSERT  0x0
  64. #define LEVEL_ASSERT    0x1
  65.  
  66. /** Destination Shorthands. */
  67. #define SHORTHAND_NONE      0x0
  68. #define SHORTHAND_SELF      0x1
  69. #define SHORTHAND_ALL_INCL  0x2
  70. #define SHORTHAND_ALL_EXCL  0x3
  71.  
  72. /** Interrupt Input Pin Polarities. */
  73. #define POLARITY_HIGH   0x0
  74. #define POLARITY_LOW    0x1
  75.  
  76. /** Divide Values. (Bit 2 is always 0) */
  77. #define DIVIDE_2    0x0
  78. #define DIVIDE_4    0x1
  79. #define DIVIDE_8    0x2
  80. #define DIVIDE_16   0x3
  81. #define DIVIDE_32   0x8
  82. #define DIVIDE_64   0x9
  83. #define DIVIDE_128  0xa
  84. #define DIVIDE_1    0xb
  85.  
  86. /** Timer Modes. */
  87. #define TIMER_ONESHOT   0x0
  88. #define TIMER_PERIODIC  0x1
  89.  
  90. /** Delivery status. */
  91. #define DELIVS_IDLE 0x0
  92. #define DELIVS_PENDING  0x1
  93.  
  94. /** Destination masks. */
  95. #define DEST_ALL    0xff
  96.  
  97. /** Dest format models. */
  98. #define MODEL_FLAT  0xf
  99. #define MODEL_CLUSTER   0x0
  100.  
  101. /** Interrupt Command Register. */
  102. #define ICRlo       (0x300/sizeof(__u32))
  103. #define ICRhi       (0x310/sizeof(__u32))
  104. struct icr {
  105.     union {
  106.         __u32 lo;
  107.         struct {
  108.             __u8 vector;            /**< Interrupt Vector. */
  109.             unsigned delmod : 3;        /**< Delivery Mode. */
  110.             unsigned destmod : 1;       /**< Destination Mode. */
  111.             unsigned delivs : 1;        /**< Delivery status (RO). */
  112.             unsigned : 1;           /**< Reserved. */
  113.             unsigned level : 1;     /**< Level. */
  114.             unsigned trigger_mode : 1;  /**< Trigger Mode. */
  115.             unsigned : 2;           /**< Reserved. */
  116.             unsigned shorthand : 2;     /**< Destination Shorthand. */
  117.             unsigned : 12;          /**< Reserved. */
  118.         } __attribute__ ((packed));
  119.     };
  120.     union {
  121.         __u32 hi;
  122.         struct {
  123.             unsigned : 24;          /**< Reserved. */
  124.             __u8 dest;          /**< Destination field. */
  125.         } __attribute__ ((packed));
  126.     };
  127. } __attribute__ ((packed));
  128. typedef struct icr icr_t;
  129.  
  130. /* End Of Interrupt. */
  131. #define EOI     (0x0b0/sizeof(__u32))
  132.  
  133. /** Error Status Register. */
  134. #define ESR     (0x280/sizeof(__u32))
  135. union esr {
  136.     __u32 value;
  137.     __u8 err_bitmap;
  138.     struct {
  139.         unsigned send_checksum_error : 1;
  140.         unsigned receive_checksum_error : 1;
  141.         unsigned send_accept_error : 1;
  142.         unsigned receive_accept_error : 1;
  143.         unsigned : 1;
  144.         unsigned send_illegal_vector : 1;
  145.         unsigned received_illegal_vector : 1;
  146.         unsigned illegal_register_address : 1;
  147.         unsigned : 24;
  148.     } __attribute__ ((packed));
  149. };
  150. typedef union esr esr_t;
  151.  
  152. /* Task Priority Register */
  153. #define TPR     (0x080/sizeof(__u32))
  154. union tpr {
  155.     __u32 value;
  156.     struct {
  157.         unsigned pri_sc : 4;        /**< Task Priority Sub-Class. */
  158.         unsigned pri : 4;       /**< Task Priority. */
  159.     } __attribute__ ((packed));
  160. };
  161. typedef union tpr tpr_t;
  162.  
  163. /** Spurious-Interrupt Vector Register. */
  164. #define SVR     (0x0f0/sizeof(__u32))
  165. union svr {
  166.     __u32 value;
  167.     struct {
  168.         __u8 vector;            /**< Spurious Vector. */
  169.         unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable. */
  170.         unsigned focus_checking : 1;    /**< Focus Processor Checking. */
  171.         unsigned : 22;          /**< Reserved. */
  172.     } __attribute__ ((packed));
  173. };
  174. typedef union svr svr_t;
  175.  
  176. /** Time Divide Configuration Register. */
  177. #define TDCR        (0x3e0/sizeof(__u32))
  178. union tdcr {
  179.     __u32 value;
  180.     struct {
  181.         unsigned div_value : 4;     /**< Divide Value, bit 2 is always 0. */
  182.         unsigned : 28;          /**< Reserved. */
  183.     } __attribute__ ((packed));
  184. };
  185. typedef union tdcr tdcr_t;
  186.  
  187. /* Initial Count Register for Timer */
  188. #define ICRT        (0x380/sizeof(__u32))
  189.  
  190. /* Current Count Register for Timer */
  191. #define CCRT        (0x390/sizeof(__u32))
  192.  
  193. /** LVT Timer register. */
  194. #define LVT_Tm      (0x320/sizeof(__u32))
  195. union lvt_tm {
  196.     __u32 value;
  197.     struct {
  198.         __u8 vector;        /**< Local Timer Interrupt vector. */
  199.         unsigned : 4;       /**< Reserved. */
  200.         unsigned delivs : 1;    /**< Delivery status (RO). */
  201.         unsigned : 3;       /**< Reserved. */
  202.         unsigned masked : 1;    /**< Interrupt Mask. */
  203.         unsigned mode : 1;  /**< Timer Mode. */
  204.         unsigned : 14;      /**< Reserved. */
  205.     } __attribute__ ((packed));
  206. };
  207. typedef union lvt_tm lvt_tm_t;
  208.  
  209. /** LVT LINT registers. */
  210. #define LVT_LINT0   (0x350/sizeof(__u32))
  211. #define LVT_LINT1   (0x360/sizeof(__u32))
  212. union lvt_lint {
  213.     __u32 value;
  214.     struct {
  215.         __u8 vector;            /**< LINT Interrupt vector. */
  216.         unsigned delmod : 3;        /**< Delivery Mode. */
  217.         unsigned : 1;           /**< Reserved. */
  218.         unsigned delivs : 1;        /**< Delivery status (RO). */
  219.         unsigned intpol : 1;        /**< Interrupt Input Pin Polarity. */
  220.         unsigned irr : 1;       /**< Remote IRR (RO). */
  221.         unsigned trigger_mode : 1;  /**< Trigger Mode. */
  222.         unsigned masked : 1;        /**< Interrupt Mask. */
  223.         unsigned : 15;          /**< Reserved. */
  224.     } __attribute__ ((packed));
  225. };
  226. typedef union lvt_lint lvt_lint_t;
  227.  
  228. /** LVT Error register. */
  229. #define LVT_Err     (0x370/sizeof(__u32))
  230. union lvt_error {
  231.     __u32 value;
  232.     struct {
  233.         __u8 vector;        /**< Local Timer Interrupt vector. */
  234.         unsigned : 4;       /**< Reserved. */
  235.         unsigned delivs : 1;    /**< Delivery status (RO). */
  236.         unsigned : 3;       /**< Reserved. */
  237.         unsigned masked : 1;    /**< Interrupt Mask. */
  238.         unsigned : 15;      /**< Reserved. */
  239.     } __attribute__ ((packed));
  240. };
  241. typedef union lvt_error lvt_error_t;
  242.  
  243. /** Local APIC ID Register. */
  244. #define L_APIC_ID   (0x020/sizeof(__u32))
  245. union l_apic_id {
  246.     __u32 value;
  247.     struct {
  248.         unsigned : 24;      /**< Reserved. */
  249.         __u8 apic_id;       /**< Local APIC ID. */
  250.     } __attribute__ ((packed));
  251. };
  252. typedef union l_apic_id l_apic_id_t;
  253.  
  254. /** Local APIC Version Register */
  255. #define LAVR        (0x030/sizeof(__u32))
  256. #define LAVR_Mask   0xff
  257. #define is_local_apic(x)    (((x)&LAVR_Mask&0xf0)==0x1)
  258. #define is_82489DX_apic(x)  ((((x)&LAVR_Mask&0xf0)==0x0))
  259. #define is_local_xapic(x)   (((x)&LAVR_Mask)==0x14)
  260.  
  261. /** Logical Destination Register. */
  262. #define  LDR        (0x0d0/sizeof(__u32))
  263. union ldr {
  264.     __u32 value;
  265.     struct {
  266.         unsigned : 24;      /**< Reserved. */
  267.         __u8 id;        /**< Logical APIC ID. */
  268.     } __attribute__ ((packed));
  269. };
  270. typedef union ldr ldr_t;
  271.  
  272. /** Destination Format Register. */
  273. #define DFR     (0x0e0/sizeof(__u32))
  274. union dfr {
  275.     __u32 value;
  276.     struct {
  277.         unsigned : 28;      /**< Reserved, all ones. */
  278.         unsigned model : 4; /**< Model. */
  279.     } __attribute__ ((packed));
  280. };
  281. typedef union dfr dfr_t;
  282.  
  283. /* IO APIC */
  284. #define IOREGSEL    (0x00/sizeof(__u32))
  285. #define IOWIN       (0x10/sizeof(__u32))
  286.  
  287. #define IOAPICID    0x00
  288. #define IOAPICVER   0x01
  289. #define IOAPICARB   0x02
  290. #define IOREDTBL    0x10
  291.  
  292. /** I/O Register Select Register. */
  293. union io_regsel {
  294.     __u32 value;
  295.     struct {
  296.         __u8 reg_addr;      /**< APIC Register Address. */
  297.         unsigned : 24;      /**< Reserved. */
  298.     } __attribute__ ((packed));
  299. };
  300. typedef union io_regsel io_regsel_t;
  301.  
  302. /** I/O Redirection Register. */
  303. struct io_redirection_reg {
  304.     union {
  305.         __u32 lo;
  306.         struct {
  307.             __u8 intvec;            /**< Interrupt Vector. */
  308.             unsigned delmod : 3;        /**< Delivery Mode. */
  309.             unsigned destmod : 1;       /**< Destination mode. */
  310.             unsigned delivs : 1;        /**< Delivery status (RO). */
  311.             unsigned intpol : 1;        /**< Interrupt Input Pin Polarity. */
  312.             unsigned irr : 1;       /**< Remote IRR (RO). */
  313.             unsigned trigger_mode : 1;  /**< Trigger Mode. */
  314.             unsigned masked : 1;        /**< Interrupt Mask. */
  315.             unsigned : 15;          /**< Reserved. */
  316.         } __attribute__ ((packed));
  317.     };
  318.     union {
  319.         __u32 hi;
  320.         struct {
  321.             unsigned : 24;          /**< Reserved. */
  322.             __u8 dest : 8;          /**< Destination Field. */
  323.         } __attribute__ ((packed));
  324.     };
  325.    
  326. } __attribute__ ((packed));
  327. typedef struct io_redirection_reg io_redirection_reg_t;
  328.  
  329.  
  330. /** IO APIC Identification Register. */
  331. union io_apic_id {
  332.     __u32 value;
  333.     struct {
  334.         unsigned : 24;      /**< Reserved. */
  335.         unsigned apic_id : 4;   /**< IO APIC ID. */
  336.         unsigned : 4;       /**< Reserved. */
  337.     } __attribute__ ((packed));
  338. };
  339. typedef union io_apic_id io_apic_id_t;
  340.  
  341. extern volatile __u32 *l_apic;
  342. extern volatile __u32 *io_apic;
  343.  
  344. extern __u32 apic_id_mask;
  345.  
  346. extern void apic_init(void);
  347.  
  348. extern void l_apic_init(void);
  349. extern void l_apic_eoi(void);
  350. extern int l_apic_broadcast_custom_ipi(__u8 vector);
  351. extern int l_apic_send_init_ipi(__u8 apicid);
  352. extern void l_apic_debug(void);
  353. extern __u8 l_apic_id(void);
  354.  
  355. extern __u32 io_apic_read(__u8 address);
  356. extern void io_apic_write(__u8 address , __u32 x);
  357. extern void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags);
  358. extern void io_apic_disable_irqs(__u16 irqmask);
  359. extern void io_apic_enable_irqs(__u16 irqmask);
  360.  
  361. #endif
  362.