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  1. /*
  2.  * Copyright (C) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #ifndef __ia32_BARRIER_H__
  30. #define __ia32_BARRIER_H__
  31.  
  32. #include <arch/types.h>
  33.  
  34. /*
  35.  * NOTE:
  36.  * No barriers for critical section (i.e. spinlock) on IA-32 are needed:
  37.  * - spinlock_lock() and spinlock_trylock() use serializing XCHG instruction
  38.  * - writes cannot pass reads on IA-32 => spinlock_unlock() needs no barriers
  39.  */
  40.  
  41. /*
  42.  * Provisions are made to prevent compiler from reordering instructions itself.
  43.  */
  44.  
  45. #define CS_ENTER_BARRIER()  __asm__ volatile ("" ::: "memory")
  46. #define CS_LEAVE_BARRIER()  __asm__ volatile ("" ::: "memory")
  47.  
  48. static inline void cpuid_serialization(void)
  49. {
  50.     __asm__ volatile (
  51.         "xorl %%eax, %%eax\n"
  52.         "cpuid\n"
  53.         ::: "eax", "ebx", "ecx", "edx", "memory"
  54.     );
  55. }
  56.  
  57. #ifdef CONFIG_FENCES_P4
  58. #   define memory_barrier()     __asm__ volatile ("mfence\n" ::: "memory")
  59. #   define read_barrier()       __asm__ volatile ("lfence\n" ::: "memory")
  60. #   ifdef CONFIG_WEAK_MEMORY
  61. #       define write_barrier()  __asm__ volatile ("sfence\n" ::: "memory")
  62. #   else
  63. #       define write_barrier()
  64. #   endif
  65. #elif CONFIG_FENCES_P3
  66. #   define memory_barrier()     cpuid_serialization()
  67. #   define read_barrier()       cpuid_serialization()
  68. #   ifdef CONFIG_WEAK_MEMORY
  69. #       define write_barrier()  __asm__ volatile ("sfence\n" ::: "memory")
  70. #   else
  71. #       define write_barrier()
  72. #   endif
  73. #else
  74. #   define memory_barrier()     cpuid_serialization()
  75. #   define read_barrier()       cpuid_serialization()
  76. #   ifdef CONFIG_WEAK_MEMORY
  77. #       define write_barrier()  cpuid_serialization()
  78. #   else
  79. #       define write_barrier()
  80. #   endif
  81. #endif
  82.  
  83. #endif
  84.