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  1. /*
  2.  * Copyright (C) 2001-2004 Jakub Jermar
  3.  * Copyright (C) 2005-2006 Ondrej Palkovsky
  4.  * All rights reserved.
  5.  *
  6.  * Redistribution and use in source and binary forms, with or without
  7.  * modification, are permitted provided that the following conditions
  8.  * are met:
  9.  *
  10.  * - Redistributions of source code must retain the above copyright
  11.  *   notice, this list of conditions and the following disclaimer.
  12.  * - Redistributions in binary form must reproduce the above copyright
  13.  *   notice, this list of conditions and the following disclaimer in the
  14.  *   documentation and/or other materials provided with the distribution.
  15.  * - The name of the author may not be used to endorse or promote products
  16.  *   derived from this software without specific prior written permission.
  17.  *
  18.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  19.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  20.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28.  */
  29.  
  30. #include <arch/pm.h>
  31. #include <arch/mm/page.h>
  32. #include <arch/types.h>
  33. #include <arch/interrupt.h>
  34. #include <arch/asm.h>
  35. #include <interrupt.h>
  36. #include <mm/as.h>
  37.  
  38. #include <config.h>
  39.  
  40. #include <memstr.h>
  41. #include <mm/slab.h>
  42. #include <debug.h>
  43.  
  44. /*
  45.  * There is no segmentation in long mode so we set up flat mode. In this
  46.  * mode, we use, for each privilege level, two segments spanning the
  47.  * whole memory. One is for code and one is for data.
  48.  */
  49.  
  50. descriptor_t gdt[GDT_ITEMS] = {
  51.     /* NULL descriptor */
  52.     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
  53.     /* KTEXT descriptor */
  54.     { .limit_0_15  = 0xffff,
  55.       .base_0_15   = 0,
  56.       .base_16_23  = 0,
  57.       .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE ,
  58.       .limit_16_19 = 0xf,
  59.       .available   = 0,
  60.       .longmode    = 1,
  61.       .special     = 0,
  62.       .granularity = 1,
  63.       .base_24_31  = 0 },
  64.     /* KDATA descriptor */
  65.     { .limit_0_15  = 0xffff,
  66.       .base_0_15   = 0,
  67.       .base_16_23  = 0,
  68.       .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL,
  69.       .limit_16_19 = 0xf,
  70.       .available   = 0,
  71.       .longmode    = 0,
  72.       .special     = 0,
  73.       .granularity = 1,
  74.       .base_24_31  = 0 },
  75.     /* UDATA descriptor */
  76.     { .limit_0_15  = 0xffff,
  77.       .base_0_15   = 0,
  78.       .base_16_23  = 0,
  79.       .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,
  80.       .limit_16_19 = 0xf,
  81.       .available   = 0,
  82.       .longmode    = 0,
  83.       .special     = 1,
  84.       .granularity = 1,
  85.       .base_24_31  = 0 },
  86.     /* UTEXT descriptor */
  87.     { .limit_0_15  = 0xffff,
  88.       .base_0_15   = 0,
  89.       .base_16_23  = 0,
  90.       .access      = AR_PRESENT | AR_CODE | DPL_USER,
  91.       .limit_16_19 = 0xf,
  92.       .available   = 0,
  93.       .longmode    = 1,
  94.       .special     = 0,
  95.       .granularity = 1,
  96.       .base_24_31  = 0 },
  97.     /* KTEXT 32-bit protected, for protected mode before long mode */
  98.     { .limit_0_15  = 0xffff,
  99.       .base_0_15   = 0,
  100.       .base_16_23  = 0,
  101.       .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
  102.       .limit_16_19 = 0xf,
  103.       .available   = 0,
  104.       .longmode    = 0,
  105.       .special     = 1,
  106.       .granularity = 1,
  107.       .base_24_31  = 0 },
  108.     /* TSS descriptor - set up will be completed later,
  109.      * on AMD64 it is 64-bit - 2 items in table */
  110.     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
  111.     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
  112. };
  113.  
  114. idescriptor_t idt[IDT_ITEMS];
  115.  
  116. ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base= (__u64) gdt };
  117. ptr_16_64_t idtr = {.limit = sizeof(idt), .base= (__u64) idt };
  118.  
  119. static tss_t tss;
  120. tss_t *tss_p = NULL;
  121.  
  122. void gdt_tss_setbase(descriptor_t *d, __address base)
  123. {
  124.     tss_descriptor_t *td = (tss_descriptor_t *) d;
  125.  
  126.     td->base_0_15 = base & 0xffff;
  127.     td->base_16_23 = ((base) >> 16) & 0xff;
  128.     td->base_24_31 = ((base) >> 24) & 0xff;
  129.     td->base_32_63 = ((base) >> 32);
  130. }
  131.  
  132. void gdt_tss_setlimit(descriptor_t *d, __u32 limit)
  133. {
  134.     struct tss_descriptor *td = (tss_descriptor_t *) d;
  135.  
  136.     td->limit_0_15 = limit & 0xffff;
  137.     td->limit_16_19 = (limit >> 16) & 0xf;
  138. }
  139.  
  140. void idt_setoffset(idescriptor_t *d, __address offset)
  141. {
  142.     /*
  143.      * Offset is a linear address.
  144.      */
  145.     d->offset_0_15 = offset & 0xffff;
  146.     d->offset_16_31 = offset >> 16 & 0xffff;
  147.     d->offset_32_63 = offset >> 32;
  148. }
  149.  
  150. void tss_initialize(tss_t *t)
  151. {
  152.     memsetb((__address) t, sizeof(tss_t), 0);
  153. }
  154.  
  155. /*
  156.  * This function takes care of proper setup of IDT and IDTR.
  157.  */
  158. void idt_init(void)
  159. {
  160.     idescriptor_t *d;
  161.     int i;
  162.  
  163.     for (i = 0; i < IDT_ITEMS; i++) {
  164.         d = &idt[i];
  165.  
  166.         d->unused = 0;
  167.         d->selector = gdtselector(KTEXT_DES);
  168.  
  169.         d->present = 1;
  170.         d->type = AR_INTERRUPT; /* masking interrupt */
  171.  
  172.         idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
  173.         exc_register(i, "undef", (iroutine)null_interrupt);
  174.     }
  175.  
  176.     exc_register( 7, "nm_fault", nm_fault);
  177.     exc_register(12, "ss_fault", ss_fault);
  178.     exc_register(13, "gp_fault", gp_fault);
  179.     exc_register(14, "ident_mapper", ident_page_fault);
  180. }
  181.  
  182. /** Initialize segmentation - code/data/idt tables
  183.  *
  184.  */
  185. void pm_init(void)
  186. {
  187.     descriptor_t *gdt_p = (struct descriptor *) gdtr.base;
  188.     tss_descriptor_t *tss_desc;
  189.  
  190.     /*
  191.      * Each CPU has its private GDT and TSS.
  192.      * All CPUs share one IDT.
  193.      */
  194.  
  195.     if (config.cpu_active == 1) {
  196.         idt_init();
  197.         /*
  198.          * NOTE: bootstrap CPU has statically allocated TSS, because
  199.          * the heap hasn't been initialized so far.
  200.          */
  201.         tss_p = &tss;
  202.     }
  203.     else {
  204.         /* We are going to use malloc, which may return
  205.          * non boot-mapped pointer, initialize the CR3 register
  206.          * ahead of page_init */
  207.         write_cr3((__address) AS_KERNEL->page_table);
  208.  
  209.         tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC);
  210.         if (!tss_p)
  211.             panic("could not allocate TSS\n");
  212.     }
  213.  
  214.     tss_initialize(tss_p);
  215.  
  216.     tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
  217.     tss_desc->present = 1;
  218.     tss_desc->type = AR_TSS;
  219.     tss_desc->dpl = PL_KERNEL;
  220.    
  221.     gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);
  222.     gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
  223.  
  224.     gdtr_load(&gdtr);
  225.     idtr_load(&idtr);
  226.     /*
  227.      * As of this moment, the current CPU has its own GDT pointing
  228.      * to its own TSS. We just need to load the TR register.
  229.      */
  230.     tr_load(gdtselector(TSS_DES));
  231. }
  232.