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  1. /*
  2.  * Copyright (C) 2001-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #include <arch/pm.h>
  30. #include <arch/mm/page.h>
  31. #include <arch/types.h>
  32. #include <arch/interrupt.h>
  33. #include <arch/asm.h>
  34. #include <interrupt.h>
  35.  
  36. #include <config.h>
  37.  
  38. #include <memstr.h>
  39. #include <mm/heap.h>
  40. #include <debug.h>
  41.  
  42. /*
  43.  * There is no segmentation in long mode so we set up flat mode. In this
  44.  * mode, we use, for each privilege level, two segments spanning the
  45.  * whole memory. One is for code and one is for data.
  46.  */
  47.  
  48. struct descriptor gdt[GDT_ITEMS] = {
  49.     /* NULL descriptor */
  50.     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
  51.     /* KTEXT descriptor */
  52.     { .limit_0_15  = 0xffff,
  53.       .base_0_15   = 0,
  54.       .base_16_23  = 0,
  55.       .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE ,
  56.       .limit_16_19 = 0xf,
  57.       .available   = 0,
  58.       .longmode    = 1,
  59.       .special     = 0,
  60.       .granularity = 1,
  61.       .base_24_31  = 0 },
  62.     /* KDATA descriptor */
  63.     { .limit_0_15  = 0xffff,
  64.       .base_0_15   = 0,
  65.       .base_16_23  = 0,
  66.       .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL,
  67.       .limit_16_19 = 0xf,
  68.       .available   = 0,
  69.       .longmode    = 0,
  70.       .special     = 0,
  71.       .granularity = 1,
  72.       .base_24_31  = 0 },
  73.     /* UTEXT descriptor */
  74.     { .limit_0_15  = 0xffff,
  75.       .base_0_15   = 0,
  76.       .base_16_23  = 0,
  77.       .access      = AR_PRESENT | AR_CODE | DPL_USER,
  78.       .limit_16_19 = 0xf,
  79.       .available   = 0,
  80.       .longmode    = 1,
  81.       .special     = 0,
  82.       .granularity = 1,
  83.       .base_24_31  = 0 },
  84.     /* UDATA descriptor */
  85.     { .limit_0_15  = 0xffff,
  86.       .base_0_15   = 0,
  87.       .base_16_23  = 0,
  88.       .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,
  89.       .limit_16_19 = 0xf,
  90.       .available   = 0,
  91.       .longmode    = 0,
  92.       .special     = 1,
  93.       .granularity = 1,
  94.       .base_24_31  = 0 },
  95.     /* KTEXT 32-bit protected, for protected mode before long mode */
  96.     { .limit_0_15  = 0xffff,
  97.       .base_0_15   = 0,
  98.       .base_16_23  = 0,
  99.       .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
  100.       .limit_16_19 = 0xf,
  101.       .available   = 0,
  102.       .longmode    = 0,
  103.       .special     = 1,
  104.       .granularity = 1,
  105.       .base_24_31  = 0 },
  106.     /* TSS descriptor - set up will be completed later,
  107.      * on AMD64 it is 64-bit - 2 items in table */
  108.     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
  109.     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
  110. };
  111.  
  112. struct idescriptor idt[IDT_ITEMS];
  113.  
  114. struct ptr_16_64 gdtr = {.limit = sizeof(gdt), .base= (__u64) gdt };
  115. struct ptr_16_64 idtr = {.limit = sizeof(idt), .base= (__u64) idt };
  116.  
  117. static struct tss tss;
  118. struct tss *tss_p = NULL;
  119.  
  120. void gdt_tss_setbase(struct descriptor *d, __address base)
  121. {
  122.     struct tss_descriptor *td = (struct tss_descriptor *) d;
  123.  
  124.     td->base_0_15 = base & 0xffff;
  125.     td->base_16_23 = ((base) >> 16) & 0xff;
  126.     td->base_24_31 = ((base) >> 24) & 0xff;
  127.     td->base_32_63 = ((base) >> 32);
  128. }
  129.  
  130. void gdt_tss_setlimit(struct descriptor *d, __u32 limit)
  131. {
  132.     struct tss_descriptor *td = (struct tss_descriptor *) d;
  133.  
  134.     td->limit_0_15 = limit & 0xffff;
  135.     td->limit_16_19 = (limit >> 16) & 0xf;
  136. }
  137.  
  138. void idt_setoffset(struct idescriptor *d, __address offset)
  139. {
  140.     /*
  141.      * Offset is a linear address.
  142.      */
  143.     d->offset_0_15 = offset & 0xffff;
  144.     d->offset_16_31 = offset >> 16 & 0xffff;
  145.     d->offset_32_63 = offset >> 32;
  146. }
  147.  
  148. void tss_initialize(struct tss *t)
  149. {
  150.     memsetb((__address) t, sizeof(struct tss), 0);
  151. }
  152.  
  153. /*
  154.  * This function takes care of proper setup of IDT and IDTR.
  155.  */
  156. void idt_init(void)
  157. {
  158.     struct idescriptor *d;
  159.     int i;
  160.  
  161.     for (i = 0; i < IDT_ITEMS; i++) {
  162.         d = &idt[i];
  163.  
  164.         d->unused = 0;
  165.         d->selector = gdtselector(KTEXT_DES);
  166.  
  167.         d->present = 1;
  168.         d->type = AR_INTERRUPT; /* masking interrupt */
  169.  
  170.         if (i == VECTOR_SYSCALL) {
  171.             /*
  172.              * The syscall interrupt gate must be calleable from userland.
  173.              */
  174.             d->dpl |= PL_USER;
  175.         }
  176.        
  177.         idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
  178.         exc_register(i, "undef", null_interrupt);
  179.     }
  180.     exc_register(13, "gp_fault", gp_fault);
  181.     exc_register( 7, "nm_fault", nm_fault);
  182.     exc_register(12, "ss_fault", ss_fault);
  183. }
  184.  
  185.  
  186. /* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
  187. static void clean_IOPL_NT_flags(void)
  188. {
  189.     asm
  190.     (
  191.         "pushfq;"
  192.         "pop %%rax;"
  193.         "and $~(0x7000),%%rax;"
  194.         "pushq %%rax;"
  195.         "popfq;"
  196.         :
  197.         :
  198.         :"%rax"
  199.     );
  200. }
  201.  
  202. /* Clean AM(18) flag in CR0 register */
  203. static void clean_AM_flag(void)
  204. {
  205.     asm
  206.     (
  207.         "mov %%cr0,%%rax;"
  208.         "and $~(0x40000),%%rax;"
  209.         "mov %%rax,%%cr0;"
  210.         :
  211.         :
  212.         :"%rax"
  213.     );
  214. }
  215.  
  216. void pm_init(void)
  217. {
  218.     struct descriptor *gdt_p = (struct descriptor *) gdtr.base;
  219.     struct tss_descriptor *tss_desc;
  220.  
  221.     /*
  222.      * Each CPU has its private GDT and TSS.
  223.      * All CPUs share one IDT.
  224.      */
  225.  
  226.     if (config.cpu_active == 1) {
  227.         idt_init();
  228.         /*
  229.          * NOTE: bootstrap CPU has statically allocated TSS, because
  230.          * the heap hasn't been initialized so far.
  231.          */
  232.         tss_p = &tss;
  233.     }
  234.     else {
  235.         tss_p = (struct tss *) malloc(sizeof(struct tss));
  236.         if (!tss_p)
  237.             panic("could not allocate TSS\n");
  238.     }
  239.  
  240.     tss_initialize(tss_p);
  241.  
  242.     tss_desc = (struct tss_descriptor *) (&gdt_p[TSS_DES]);
  243.     tss_desc->present = 1;
  244.     tss_desc->type = AR_TSS;
  245.     tss_desc->dpl = PL_KERNEL;
  246.    
  247.     gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);
  248.     gdt_tss_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1);
  249.  
  250.     __asm__("lgdt %0" : : "m"(gdtr));
  251.     __asm__("lidt %0" : : "m"(idtr));
  252.     /*
  253.      * As of this moment, the current CPU has its own GDT pointing
  254.      * to its own TSS. We just need to load the TR register.
  255.      */
  256.     __asm__("ltr %0" : : "r" ((__u16) gdtselector(TSS_DES)));
  257.    
  258.     clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels */
  259.     clean_AM_flag();          /* Disable alignment check */
  260. }
  261.