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  1. /*
  2.  * Copyright (C) 2005 Ondrej Palkovsky
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #include <arch.h>
  30.  
  31. #include <arch/types.h>
  32.  
  33. #include <config.h>
  34.  
  35. #include <proc/thread.h>
  36. #include <arch/ega.h>
  37. #include <arch/vesa.h>
  38. #include <genarch/i8042/i8042.h>
  39. #include <arch/i8254.h>
  40. #include <arch/i8259.h>
  41.  
  42. #include <arch/bios/bios.h>
  43. #include <arch/mm/memory_init.h>
  44. #include <arch/cpu.h>
  45. #include <print.h>
  46. #include <arch/cpuid.h>
  47. #include <genarch/acpi/acpi.h>
  48. #include <panic.h>
  49. #include <interrupt.h>
  50. #include <arch/syscall.h>
  51. #include <arch/debugger.h>
  52. #include <syscall/syscall.h>
  53.  
  54.  
  55. /** Disable I/O on non-privileged levels
  56.  *
  57.  * Clean IOPL(12,13) and NT(14) flags in EFLAGS register
  58.  */
  59. static void clean_IOPL_NT_flags(void)
  60. {
  61.     asm
  62.     (
  63.         "pushfq;"
  64.         "pop %%rax;"
  65.         "and $~(0x7000),%%rax;"
  66.         "pushq %%rax;"
  67.         "popfq;"
  68.         :
  69.         :
  70.         :"%rax"
  71.     );
  72. }
  73.  
  74. /** Disable alignment check
  75.  *
  76.  * Clean AM(18) flag in CR0 register
  77.  */
  78. static void clean_AM_flag(void)
  79. {
  80.     asm
  81.     (
  82.         "mov %%cr0,%%rax;"
  83.         "and $~(0x40000),%%rax;"
  84.         "mov %%rax,%%cr0;"
  85.         :
  86.         :
  87.         :"%rax"
  88.     );
  89. }
  90.  
  91. void arch_pre_mm_init(void)
  92. {
  93.     struct cpu_info cpuid_s;
  94.  
  95.     cpuid(AMD_CPUID_EXTENDED,&cpuid_s);
  96.     if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE)))
  97.         panic("Processor does not support No-execute pages.\n");
  98.  
  99.     cpuid(INTEL_CPUID_STANDARD,&cpuid_s);
  100.     if (! (cpuid_s.cpuid_edx & (1<<INTEL_FXSAVE)))
  101.         panic("Processor does not support FXSAVE/FXRESTORE.\n");
  102.    
  103.     if (! (cpuid_s.cpuid_edx & (1<<INTEL_SSE2)))
  104.         panic("Processor does not support SSE2 instructions.\n");
  105.  
  106.     /* Enable No-execute pages */
  107.     set_efer_flag(AMD_NXE_FLAG);
  108.     /* Enable FPU */
  109.     cpu_setup_fpu();
  110.  
  111.     /* Initialize segmentation */
  112.     pm_init();
  113.  
  114.         /* Disable I/O on nonprivileged levels
  115.      * clear the NT(nested-thread) flag
  116.      */
  117.     clean_IOPL_NT_flags();
  118.     /* Disable alignment check */
  119.     clean_AM_flag();
  120.  
  121.     if (config.cpu_active == 1) {
  122.         bios_init();
  123.         i8259_init();   /* PIC */
  124.         i8254_init();   /* hard clock */
  125.  
  126.         #ifdef CONFIG_SMP
  127.         exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown",
  128.                  tlb_shootdown_ipi);
  129.         #endif /* CONFIG_SMP */
  130.     }
  131. }
  132.  
  133. void arch_post_mm_init(void)
  134. {
  135.     if (config.cpu_active == 1) {
  136. #ifdef CONFIG_FB
  137.     if (vesa_present()) vesa_init();
  138.     else
  139. #endif
  140.         ega_init(); /* video */
  141.         /* Enable debugger */
  142.         debugger_init();
  143.     }
  144.     /* Setup fast SYSCALL/SYSRET */
  145.     syscall_setup_cpu();
  146.    
  147. }
  148.  
  149. void arch_pre_smp_init(void)
  150. {
  151.     if (config.cpu_active == 1) {
  152.         memory_print_map();
  153.        
  154.         #ifdef CONFIG_SMP
  155.         acpi_init();
  156.         #endif /* CONFIG_SMP */
  157.     }
  158. }
  159.  
  160. void arch_post_smp_init(void)
  161. {
  162.     i8042_init();   /* keyboard controller */
  163. }
  164.  
  165. void calibrate_delay_loop(void)
  166. {
  167.     i8254_calibrate_delay_loop();
  168.     i8254_normal_operation();
  169. }
  170.  
  171. /** Set thread-local-storage pointer
  172.  *
  173.  * TLS pointer is set in FS register. Unfortunately the 64-bit
  174.  * part can be set only in CPL0 mode.
  175.  *
  176.  * The specs say, that on %fs:0 there is stored contents of %fs register,
  177.  * we need not to go to CPL0 to read it.
  178.  */
  179. __native sys_tls_set(__native addr)
  180. {
  181.     THREAD->arch.tls = addr;
  182.     write_msr(AMD_MSR_FS, addr);
  183.     return 0;
  184. }
  185.