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  1. /*
  2.  * Copyright (C) 2001-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #ifdef __SMP__
  30.  
  31. #include <arch/types.h>
  32. #include <arch/apic.h>
  33. #include <arch/ap.h>
  34. #include <mm/page.h>
  35. #include <time/delay.h>
  36. #include <arch/interrupt.h>
  37. #include <print.h>
  38. #include <arch/mp.h>
  39. #include <arch/asm.h>
  40. #include <arch.h>
  41.  
  42. /*
  43.  * This is functional, far-from-general-enough interface to the APIC.
  44.  * Advanced Programmable Interrupt Controller for MP systems.
  45.  * Tested on:
  46.  *  Bochs 2.0.2 with 2-8 CPUs
  47.  *  ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
  48.  */
  49.  
  50. /*
  51.  * These variables either stay configured as initilalized, or are changed by
  52.  * the MP configuration code.
  53.  *
  54.  * Pay special attention to the volatile keyword. Without it, gcc -O2 would
  55.  * optimize the code too much and accesses to l_apic and io_apic, that must
  56.  * always be 32-bit, would use byte oriented instructions.
  57.  */
  58. volatile __u32 *l_apic = (__u32 *) 0xfee00000;
  59. volatile __u32 *io_apic = (__u32 *) 0xfec00000;
  60.  
  61. __u32 apic_id_mask = 0;
  62.  
  63. int apic_poll_errors(void);
  64.  
  65. void apic_init(void)
  66. {
  67.     __u32 tmp, id, i;
  68.  
  69.     trap_register(VECTOR_APIC_SPUR, apic_spurious);
  70.  
  71.     enable_irqs_function = io_apic_enable_irqs;
  72.     disable_irqs_function = io_apic_disable_irqs;
  73.     eoi_function = l_apic_eoi;
  74.    
  75.     /*
  76.      * Configure interrupt routing.
  77.      * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
  78.      * Other interrupts will be forwarded to the lowest priority CPU.
  79.      */
  80.     io_apic_disable_irqs(0xffff);
  81.     trap_register(VECTOR_CLK, l_apic_timer_interrupt);
  82.     for (i=1; i<16; i++) {
  83.         int pin;
  84.    
  85.         if ((pin = mp_irq_to_pin(i)) != -1)
  86.                 io_apic_change_ioredtbl(pin,0xf,IVT_IRQBASE+i,LOPRI);
  87.     }
  88.    
  89.  
  90.     /*
  91.      * Ensure that io_apic has unique ID.
  92.      */
  93.     tmp = io_apic_read(IOAPICID);
  94.     id = (tmp >> 24) & 0xf;
  95.     if ((1<<id) & apic_id_mask) {
  96.         int i;
  97.        
  98.         for (i=0; i<15; i++) {
  99.             if (!((1<<i) & apic_id_mask)) {
  100.                 io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) | (i<<24));
  101.                 break;
  102.             }
  103.         }
  104.     }
  105.  
  106.  
  107.  
  108.     /*
  109.      * Configure the BSP's lapic.
  110.      */
  111.     l_apic_init();
  112.     l_apic_debug();
  113. }
  114.  
  115. void apic_spurious(__u8 n, __u32 stack[])
  116. {
  117.     printf("cpu%d: APIC spurious interrupt\n", the->cpu->id);
  118. }
  119.  
  120. int apic_poll_errors(void)
  121. {
  122.     __u32 esr;
  123.    
  124.     esr = l_apic[ESR] & ~ESRClear;
  125.    
  126.     if ((esr>>0) & 1)
  127.         printf("Send CS Error\n");
  128.     if ((esr>>1) & 1)
  129.         printf("Receive CS Error\n");
  130.     if ((esr>>2) & 1)
  131.         printf("Send Accept Error\n");
  132.     if ((esr>>3) & 1)
  133.         printf("Receive Accept Error\n");
  134.     if ((esr>>5) & 1)
  135.         printf("Send Illegal Vector\n");
  136.     if ((esr>>6) & 1)
  137.         printf("Received Illegal Vector\n");
  138.     if ((esr>>7) & 1)
  139.         printf("Illegal Register Address\n");
  140.    
  141.     return !esr;
  142. }
  143.  
  144. /*
  145.  * Universal Start-up Algorithm for bringing up the AP processors.
  146.  */
  147. int l_apic_send_init_ipi(__u8 apicid)
  148. {
  149.     __u32 lo, hi;
  150.     int i;
  151.  
  152.     /*
  153.      * Read the ICR register in and zero all non-reserved fields.
  154.      */
  155.     lo = l_apic[ICRlo] & ICRloClear;
  156.     hi = l_apic[ICRhi] & ICRhiClear;
  157.    
  158.     lo |= DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
  159.     hi |= apicid << 24;
  160.    
  161.     l_apic[ICRhi] = hi;
  162.     l_apic[ICRlo] = lo;
  163.    
  164.     /*
  165.      * According to MP Specification, 20us should be enough to
  166.      * deliver the IPI.
  167.      */
  168.     delay(20);
  169.  
  170.     if (!apic_poll_errors()) return 0;
  171.  
  172.     lo = l_apic[ICRlo] & ICRloClear;
  173.     if (lo & SEND_PENDING)
  174.         printf("IPI is pending.\n");
  175.    
  176.     l_apic[ICRlo] = lo | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
  177.  
  178.     /*
  179.      * Wait 10ms as MP Specification specifies.
  180.      */
  181.     delay(10000);
  182.  
  183.     /*
  184.      * MP specification says this should not be done for 82489DX-based
  185.      * l_apic's. However, everything is ok as long as STARTUP IPI is ignored
  186.      * by 8249DX.
  187.      */
  188.     for (i = 0; i < 2; i++) {
  189.         lo = l_apic[ICRlo] & ICRloClear;
  190.         lo |= ((__address) ap_boot) / 4096; /* calculate the reset vector */
  191.         l_apic[ICRlo] = lo | DLVRMODE_STUP | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST |  TRGRMODE_LEVEL;
  192.         delay(200);
  193.     }
  194.    
  195.     return apic_poll_errors();
  196. }
  197.  
  198. void l_apic_init(void)
  199. {
  200.     __u32 tmp, t1, t2;
  201.    
  202.  
  203.     l_apic[LVT_Err] |= (1<<16);
  204.     l_apic[LVT_LINT0] |= (1<<16);
  205.     l_apic[LVT_LINT1] |= (1<<16);
  206.  
  207.     tmp = l_apic[SVR] & SVRClear;
  208.     l_apic[SVR] = tmp | (1<<8) | (VECTOR_APIC_SPUR);
  209.  
  210.     l_apic[TPR] &= TPRClear;
  211.  
  212.     if (the->cpu->arch.family >= 6)
  213.         enable_l_apic_in_msr();
  214.    
  215.     tmp = l_apic[ICRlo] & ICRloClear;
  216.     l_apic[ICRlo] = tmp | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_INCL | TRGRMODE_LEVEL;
  217.    
  218.     /*
  219.      * Program the timer for periodic mode and respective vector.
  220.      */
  221.  
  222.     l_apic[TDCR] &= TDCRClear;
  223.     l_apic[TDCR] |= 0xb;
  224.     tmp = l_apic[LVT_Tm] | (1<<17) | (VECTOR_CLK);
  225.     l_apic[LVT_Tm] = tmp & ~(1<<16);
  226.  
  227.     t1 = l_apic[CCRT];
  228.     l_apic[ICRT] = 0xffffffff;
  229.  
  230.     while (l_apic[CCRT] == t1)
  231.         ;
  232.        
  233.     t1 = l_apic[CCRT];
  234.     delay(1000);
  235.     t2 = l_apic[CCRT];
  236.    
  237.     l_apic[ICRT] = t1-t2;
  238. }
  239.  
  240. void l_apic_eoi(void)
  241. {
  242.     l_apic[EOI] = 0;
  243. }
  244.  
  245. void l_apic_debug(void)
  246. {
  247. #ifdef LAPIC_VERBOSE
  248.     int i, lint;
  249.  
  250.     printf("LVT on cpu%d, LAPIC ID: %d\n", the->cpu->id, (l_apic[L_APIC_ID] >> 24)&0xf);
  251.  
  252.     printf("LVT_Tm: ");
  253.     if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(',');   
  254.     if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
  255.     if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
  256.     printf("%B\n", l_apic[LVT_Tm] & 0xff);
  257.    
  258.     for (i=0; i<2; i++) {
  259.         lint = i ? LVT_LINT1 : LVT_LINT0;
  260.         printf("LVT_LINT%d: ", i);
  261.         if (l_apic[lint] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
  262.         if (l_apic[lint] & (1<<15)) printf("level"); else printf("edge"); putchar(',');
  263.         printf("%d", l_apic[lint] & (1<<14)); putchar(',');
  264.         printf("%d", l_apic[lint] & (1<<13)); putchar(',');
  265.         if (l_apic[lint] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
  266.    
  267.         switch ((l_apic[lint]>>8)&7) {
  268.             case 0: printf("fixed"); break;
  269.             case 4: printf("NMI"); break;
  270.             case 7: printf("ExtINT"); break;
  271.         }
  272.         putchar(',');
  273.         printf("%B\n", l_apic[lint] & 0xff);   
  274.     }
  275.  
  276.     printf("LVT_Err: ");
  277.     if (l_apic[LVT_Err] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
  278.     if (l_apic[LVT_Err] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
  279.     printf("%B\n", l_apic[LVT_Err] & 0xff);
  280.  
  281.     /*
  282.      * This register is supported only on P6 and higher.
  283.      */
  284.     if (the->cpu->family > 5) {
  285.         printf("LVT_PCINT: ");
  286.         if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
  287.         if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
  288.         switch ((l_apic[LVT_PCINT] >> 8)&7) {
  289.             case 0: printf("fixed"); break;
  290.             case 4: printf("NMI"); break;
  291.             case 7: printf("ExtINT"); break;
  292.         }
  293.         putchar(',');
  294.         printf("%B\n", l_apic[LVT_PCINT] & 0xff);
  295.     }
  296. #endif
  297. }
  298.  
  299. void l_apic_timer_interrupt(__u8 n, __u32 stack[])
  300. {
  301.     l_apic_eoi();
  302.     clock();
  303. }
  304.  
  305. __u32 io_apic_read(__u8 address)
  306. {
  307.     __u32 tmp;
  308.    
  309.     tmp = io_apic[IOREGSEL] & ~0xf;
  310.     io_apic[IOREGSEL] = tmp | address;
  311.     return io_apic[IOWIN];
  312. }
  313.  
  314. void io_apic_write(__u8 address, __u32 x)
  315. {
  316.     __u32 tmp;
  317.  
  318.     tmp = io_apic[IOREGSEL] & ~0xf;
  319.     io_apic[IOREGSEL] = tmp | address;
  320.     io_apic[IOWIN] = x;
  321. }
  322.  
  323. void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags)
  324. {
  325.     __u32 reglo, reghi;
  326.     int dlvr = 0;
  327.    
  328.     if (flags & LOPRI)
  329.         dlvr = 1;
  330.    
  331.     reglo = io_apic_read(IOREDTBL + signal*2);
  332.     reghi = io_apic_read(IOREDTBL + signal*2 + 1);
  333.    
  334.     reghi &= ~0x0f000000;
  335.     reghi |= (dest<<24);
  336.  
  337.     reglo &= (~0x1ffff) | (1<<16); /* don't touch the mask */
  338.     reglo |= (0<<15) | (0<<13) | (0<<11) | (dlvr<<8) | v;
  339.  
  340.     io_apic_write(IOREDTBL + signal*2, reglo);     
  341.     io_apic_write(IOREDTBL + signal*2 + 1, reghi);
  342. }
  343.  
  344. void io_apic_disable_irqs(__u16 irqmask)
  345. {
  346.     int i,pin;
  347.     __u32 reglo;
  348.    
  349.     for (i=0;i<16;i++) {
  350.         if ((irqmask>>i) & 1) {
  351.             /*
  352.              * Mask the signal input in IO APIC if there is a
  353.              * mapping for the respective IRQ number.
  354.              */
  355.             pin = mp_irq_to_pin(i);
  356.             if (pin != -1) {
  357.                 reglo = io_apic_read(IOREDTBL + pin*2);
  358.                 reglo |= (1<<16);
  359.                 io_apic_write(IOREDTBL + pin*2,reglo);
  360.             }
  361.            
  362.         }
  363.     }
  364. }
  365.  
  366. void io_apic_enable_irqs(__u16 irqmask)
  367. {
  368.     int i,pin;
  369.     __u32 reglo;
  370.    
  371.     for (i=0;i<16;i++) {
  372.         if ((irqmask>>i) & 1) {
  373.             /*
  374.              * Unmask the signal input in IO APIC if there is a
  375.              * mapping for the respective IRQ number.
  376.              */
  377.             pin = mp_irq_to_pin(i);
  378.             if (pin != -1) {
  379.                 reglo = io_apic_read(IOREDTBL + pin*2);
  380.                 reglo &= ~(1<<16);
  381.                 io_apic_write(IOREDTBL + pin*2,reglo);
  382.             }
  383.            
  384.         }
  385.     }
  386.  
  387. }
  388.  
  389. #endif /* __SMP__ */
  390.