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  1. /*
  2.  * Copyright (c) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup sparc64interrupt
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #include <arch/interrupt.h>
  36. #include <arch/sparc64.h>
  37. #include <arch/trap/interrupt.h>
  38. #include <interrupt.h>
  39. #include <ddi/irq.h>
  40. #include <arch/types.h>
  41. #include <debug.h>
  42. #include <arch/asm.h>
  43. #include <arch/barrier.h>
  44. #include <print.h>
  45. #include <arch.h>
  46. #include <mm/tlb.h>
  47. #include <arch/mm/cache.h>
  48. #include <config.h>
  49. #include <synch/spinlock.h>
  50.  
  51. /** Register Interrupt Level Handler.
  52.  *
  53.  * @param n Interrupt Level (1 - 15).
  54.  * @param name Short descriptive string.
  55.  * @param f Handler.
  56.  */
  57. void interrupt_register(int n, const char *name, iroutine f)
  58. {
  59.     ASSERT(n >= IVT_FIRST && n <= IVT_ITEMS);
  60.    
  61.     exc_register(n - 1, name, f);
  62. }
  63.  
  64. /** Process hardware interrupt.
  65.  *
  66.  * @param n Ignored.
  67.  * @param istate Ignored.
  68.  */
  69. void interrupt(int n, istate_t *istate)
  70. {
  71.     uint64_t intrcv;
  72.     uint64_t data0;
  73.  
  74.     intrcv = asi_u64_read(ASI_INTR_RECEIVE, 0);
  75.     data0 = asi_u64_read(ASI_UDB_INTR_R, ASI_UDB_INTR_R_DATA_0);
  76.  
  77.     irq_t *irq = irq_dispatch_and_lock(data0);
  78.     if (irq) {
  79.         /*
  80.          * The IRQ handler was found.
  81.          */
  82.         irq->handler(irq, irq->arg);
  83.         spinlock_unlock(&irq->lock);
  84.     } else if (data0 > config.base) {
  85.         /*
  86.          * This is a cross-call.
  87.          * data0 contains address of the kernel function.
  88.          * We call the function only after we verify
  89.          * it is one of the supported ones.
  90.          */
  91. #ifdef CONFIG_SMP
  92.         if (data0 == (uintptr_t) tlb_shootdown_ipi_recv) {
  93.             tlb_shootdown_ipi_recv();
  94. #ifdef CONFIG_VIRT_IDX_DCACHE
  95.         } else if (data0 == (uintptr_t) dcache_shootdown_ipi_recv) {
  96.             dcache_shootdown_ipi_recv();
  97. #endif
  98.         }
  99. #endif
  100.     } else {
  101.         /*
  102.          * Spurious interrupt.
  103.          */
  104. #ifdef CONFIG_DEBUG
  105.         printf("cpu%d: spurious interrupt (intrcv=%#llx, "
  106.             "data0=%#llx)\n", CPU->id, intrcv, data0);
  107. #endif
  108.     }
  109.  
  110.     membar();
  111.     asi_u64_write(ASI_INTR_RECEIVE, 0, 0);
  112. }
  113.  
  114. /** @}
  115.  */
  116.