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  1. /*
  2.  * Copyright (C) 2006 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup sparc64
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #include <smp/ipi.h>
  36. #include <cpu.h>
  37. #include <arch/cpu.h>
  38. #include <arch/asm.h>
  39. #include <config.h>
  40. #include <mm/tlb.h>
  41. #include <arch/mm/cache.h>
  42. #include <arch/interrupt.h>
  43. #include <arch/trap/interrupt.h>
  44. #include <arch/barrier.h>
  45. #include <preemption.h>
  46. #include <time/delay.h>
  47. #include <panic.h>
  48.  
  49. /** Invoke function on another processor.
  50.  *
  51.  * Currently, only functions without arguments are supported.
  52.  * Supporting more arguments in the future should be no big deal.
  53.  *
  54.  * Interrupts must be disabled prior to this call.
  55.  *
  56.  * @param mid MID of the target processor.
  57.  * @param func Function to be invoked.
  58.  */
  59. static void cross_call(int mid, void (* func)(void))
  60. {
  61.     uint64_t status;
  62.     bool done;
  63.  
  64.     /*
  65.      * This functin might enable interrupts for a while.
  66.      * In order to prevent migration to another processor,
  67.      * we explicitly disable preemption.
  68.      */
  69.    
  70.     preemption_disable();
  71.    
  72.     status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
  73.     if (status & INTR_DISPATCH_STATUS_BUSY)
  74.         panic("Interrupt Dispatch Status busy bit set\n");
  75.    
  76.     do {
  77.         asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t) func);
  78.         asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);
  79.         asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);
  80.         asi_u64_write(ASI_UDB_INTR_W, (mid << INTR_VEC_DISPATCH_MID_SHIFT) | ASI_UDB_INTR_W_DISPATCH, 0);
  81.    
  82.         membar();
  83.        
  84.         do {
  85.             status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
  86.         } while (status & INTR_DISPATCH_STATUS_BUSY);
  87.        
  88.         done = !(status & INTR_DISPATCH_STATUS_NACK);
  89.         if (!done) {
  90.             /*
  91.              * Prevent deadlock.
  92.              */        
  93.             (void) interrupts_enable();
  94.             delay(20 + (tick_read() & 0xff));
  95.             (void) interrupts_disable();
  96.         }
  97.     } while (done);
  98.    
  99.     preemption_enable();
  100. }
  101.  
  102. /*
  103.  * Deliver IPI to all processors except the current one.
  104.  *
  105.  * The sparc64 architecture does not support any group addressing
  106.  * which is found, for instance, on ia32 and amd64. Therefore we
  107.  * need to simulate the broadcast by sending the message to
  108.  * all target processors step by step.
  109.  *
  110.  * We assume that interrupts are disabled.
  111.  *
  112.  * @param ipi IPI number.
  113.  */
  114. void ipi_broadcast_arch(int ipi)
  115. {
  116.     int i;
  117.    
  118.     void (* func)(void);
  119.    
  120.     switch (ipi) {
  121.     case IPI_TLB_SHOOTDOWN:
  122.         func = tlb_shootdown_ipi_recv;
  123.         break;
  124.     case IPI_DCACHE_SHOOTDOWN:
  125.         func = dcache_shootdown_ipi_recv;
  126.         break;
  127.     default:
  128.         panic("Unknown IPI (%d).\n", ipi);
  129.         break;
  130.     }
  131.    
  132.     /*
  133.      * As long as we don't support hot-plugging
  134.      * or hot-unplugging of CPUs, we can walk
  135.      * the cpus array and read processor's MID
  136.      * without locking.
  137.      */
  138.    
  139.     for (i = 0; i < config.cpu_active; i++) {
  140.         if (&cpus[i] == CPU)
  141.             continue;       /* skip the current CPU */
  142.  
  143.         cross_call(cpus[i].arch.mid, func);
  144.     }
  145. }
  146.  
  147. /** @}
  148.  */
  149.