Subversion Repositories HelenOS

Rev

Rev 1848 | Go to most recent revision | Blame | Last modification | View Log | Download | RSS feed

  1. /*
  2.  * Copyright (C) 2006 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup sparc64
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #ifndef KERN_sparc64_Z8530_H_
  36. #define KERN_sparc64_Z8530_H_
  37.  
  38. #include <arch/types.h>
  39. #include <typedefs.h>
  40. #include <arch/drivers/kbd.h>
  41.  
  42. #define Z8530_CHAN_A    4
  43. #define Z8530_CHAN_B    0
  44.  
  45. #define WR0 0
  46. #define WR1 1
  47. #define WR2 2
  48. #define WR3 3
  49. #define WR4 4
  50. #define WR5 5
  51. #define WR6 6
  52. #define WR7 7
  53. #define WR8 8
  54. #define WR9 9
  55. #define WR10    10
  56. #define WR11    11
  57. #define WR12    12
  58. #define WR13    13
  59. #define WR14    14
  60. #define WR15    15
  61.  
  62. #define RR0 0
  63. #define RR1 1
  64. #define RR2 2
  65. #define RR3 3
  66. #define RR8 8
  67. #define RR10    10
  68. #define RR12    12
  69. #define RR13    13
  70. #define RR14    14
  71. #define RR15    15
  72.  
  73. /* Write Register 0 */
  74. #define WR0_ERR_RST (0x6<<3)
  75.  
  76. /* Write Register 1 */
  77. #define WR1_RID     (0x0<<3)    /** Receive Interrupts Disabled. */
  78. #define WR1_RIFCSC  (0x1<<3)    /** Receive Interrupt on First Character or Special Condition. */
  79. #define WR1_IARCSC  (0x2<<3)    /** Interrupt on All Receive Characters or Special Conditions. */
  80. #define WR1_RISC    (0x3<<3)    /** Receive Interrupt on Special Condition. */
  81. #define WR1_PISC    (0x1<<2)    /** Parity Is Special Condition. */
  82.  
  83. /* Write Register 3 */
  84. #define WR3_RX_ENABLE   (0x1<<0)    /** Rx Enable. */
  85. #define WR3_RX8BITSCH   (0x3<<6)    /** 8-bits per character. */
  86.  
  87. /* Write Register 9 */
  88. #define WR9_MIE     (0x1<<3)    /** Master Interrupt Enable. */
  89.  
  90. /* Read Register 0 */
  91. #define RR0_RCA     (0x1<<0)    /** Receive Character Available. */
  92.  
  93. static inline void z8530_write(index_t chan, uint8_t reg, uint8_t val)
  94. {
  95.     /*
  96.      * Registers 8-15 will automatically issue the Point High
  97.      * command as their bit 3 is 1.
  98.      */
  99.     kbd_virt_address[WR0+chan] = reg;   /* select register */
  100.     kbd_virt_address[WR0+chan] = val;   /* write value */
  101. }
  102.  
  103. static inline void z8530_write_a(uint8_t reg, uint8_t val)
  104. {
  105.     z8530_write(Z8530_CHAN_A, reg, val);
  106. }
  107. static inline void z8530_write_b(uint8_t reg, uint8_t val)
  108. {
  109.     z8530_write(Z8530_CHAN_B, reg, val);
  110. }
  111.  
  112. static inline uint8_t z8530_read(index_t chan, uint8_t reg)
  113. {
  114.     /*
  115.      * Registers 8-15 will automatically issue the Point High
  116.      * command as their bit 3 is 1.
  117.      */
  118.     kbd_virt_address[WR0+chan] = reg;   /* select register */
  119.     return kbd_virt_address[WR0+chan];
  120. }
  121.  
  122. static inline uint8_t z8530_read_a(uint8_t reg)
  123. {
  124.     return z8530_read(Z8530_CHAN_A, reg);
  125. }
  126. static inline uint8_t z8530_read_b(uint8_t reg)
  127. {
  128.     return z8530_read(Z8530_CHAN_B, reg);
  129. }
  130.  
  131. #endif
  132.  
  133. /** @}
  134.  */
  135.