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  1. /*
  2.  * Copyright (C) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup sparc64
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #ifndef KERN_sparc64_BARRIER_H_
  36. #define KERN_sparc64_BARRIER_H_
  37.  
  38. /*
  39.  * TODO: Implement true SPARC V9 memory barriers for macros below.
  40.  */
  41. #define CS_ENTER_BARRIER()  __asm__ volatile ("" ::: "memory")
  42. #define CS_LEAVE_BARRIER()  __asm__ volatile ("" ::: "memory")
  43.  
  44. #define memory_barrier()    __asm__ volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory")
  45. #define read_barrier()      __asm__ volatile ("membar #LoadLoad\n" ::: "memory")
  46. #define write_barrier()     __asm__ volatile ("membar #StoreStore\n" ::: "memory")
  47.  
  48. /** Flush Instruction Memory instruction. */
  49. static inline void flush(void)
  50. {
  51.     /*
  52.      * The FLUSH instruction takes address parameter.
  53.      * As such, it may trap if the address is not found in DTLB.
  54.      *
  55.      * The entire kernel text is mapped by a locked ITLB and
  56.      * DTLB entries. Therefore, when this function is called,
  57.      * the %o7 register will always be in the range mapped by
  58.      * DTLB.
  59.      */
  60.      
  61.         __asm__ volatile ("flush %o7\n");
  62. }
  63.  
  64. /** Memory Barrier instruction. */
  65. static inline void membar(void)
  66. {
  67.     __asm__ volatile ("membar #Sync\n");
  68. }
  69.  
  70. #endif
  71.  
  72. /** @}
  73.  */
  74.