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  1. /*
  2.  * Copyright (c) 2001-2004 Jakub Jermar
  3.  * Copyright (c) 2005 Sergey Bondari
  4.  * All rights reserved.
  5.  *
  6.  * Redistribution and use in source and binary forms, with or without
  7.  * modification, are permitted provided that the following conditions
  8.  * are met:
  9.  *
  10.  * - Redistributions of source code must retain the above copyright
  11.  *   notice, this list of conditions and the following disclaimer.
  12.  * - Redistributions in binary form must reproduce the above copyright
  13.  *   notice, this list of conditions and the following disclaimer in the
  14.  *   documentation and/or other materials provided with the distribution.
  15.  * - The name of the author may not be used to endorse or promote products
  16.  *   derived from this software without specific prior written permission.
  17.  *
  18.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  19.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  20.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28.  */
  29.  
  30. /** @addtogroup ia32   
  31.  * @{
  32.  */
  33. /** @file
  34.  */
  35.  
  36. #ifndef KERN_ia32_ASM_H_
  37. #define KERN_ia32_ASM_H_
  38.  
  39. #include <arch/pm.h>
  40. #include <arch/types.h>
  41. #include <config.h>
  42.  
  43. extern uint32_t interrupt_handler_size;
  44.  
  45. extern void paging_on(void);
  46.  
  47. extern void interrupt_handlers(void);
  48.  
  49. extern void enable_l_apic_in_msr(void);
  50.  
  51.  
  52. extern void asm_delay_loop(uint32_t t);
  53. extern void asm_fake_loop(uint32_t t);
  54.  
  55.  
  56. /** Halt CPU
  57.  *
  58.  * Halt the current CPU until interrupt event.
  59.  */
  60. static inline void cpu_halt(void)
  61. {
  62.     asm("hlt\n");
  63. };
  64.  
  65. static inline void cpu_sleep(void)
  66. {
  67.     asm("hlt\n");
  68. };
  69.  
  70. #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
  71.     { \
  72.     unative_t res; \
  73.     asm volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
  74.     return res; \
  75.     }
  76.  
  77. #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
  78.     { \
  79.     asm volatile ("movl %0, %%" #reg : : "r" (regn)); \
  80.     }
  81.  
  82. GEN_READ_REG(cr0);
  83. GEN_READ_REG(cr2);
  84. GEN_READ_REG(cr3);
  85. GEN_WRITE_REG(cr3);
  86.  
  87. GEN_READ_REG(dr0);
  88. GEN_READ_REG(dr1);
  89. GEN_READ_REG(dr2);
  90. GEN_READ_REG(dr3);
  91. GEN_READ_REG(dr6);
  92. GEN_READ_REG(dr7);
  93.  
  94. GEN_WRITE_REG(dr0);
  95. GEN_WRITE_REG(dr1);
  96. GEN_WRITE_REG(dr2);
  97. GEN_WRITE_REG(dr3);
  98. GEN_WRITE_REG(dr6);
  99. GEN_WRITE_REG(dr7);
  100.  
  101. /** Byte to port
  102.  *
  103.  * Output byte to port
  104.  *
  105.  * @param port Port to write to
  106.  * @param val Value to write
  107.  */
  108. static inline void outb(uint16_t port, uint8_t val)
  109. {
  110.     asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) );
  111. }
  112.  
  113. /** Word to port
  114.  *
  115.  * Output word to port
  116.  *
  117.  * @param port Port to write to
  118.  * @param val Value to write
  119.  */
  120. static inline void outw(uint16_t port, uint16_t val)
  121. {
  122.     asm volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) );
  123. }
  124.  
  125. /** Double word to port
  126.  *
  127.  * Output double word to port
  128.  *
  129.  * @param port Port to write to
  130.  * @param val Value to write
  131.  */
  132. static inline void outl(uint16_t port, uint32_t val)
  133. {
  134.     asm volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) );
  135. }
  136.  
  137. /** Byte from port
  138.  *
  139.  * Get byte from port
  140.  *
  141.  * @param port Port to read from
  142.  * @return Value read
  143.  */
  144. static inline uint8_t inb(uint16_t port)
  145. {
  146.     uint8_t val;
  147.    
  148.     asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) );
  149.     return val;
  150. }
  151.  
  152. /** Word from port
  153.  *
  154.  * Get word from port
  155.  *
  156.  * @param port Port to read from
  157.  * @return Value read
  158.  */
  159. static inline uint16_t inw(uint16_t port)
  160. {
  161.     uint16_t val;
  162.    
  163.     asm volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) );
  164.     return val;
  165. }
  166.  
  167. /** Double word from port
  168.  *
  169.  * Get double word from port
  170.  *
  171.  * @param port Port to read from
  172.  * @return Value read
  173.  */
  174. static inline uint32_t inl(uint16_t port)
  175. {
  176.     uint32_t val;
  177.    
  178.     asm volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) );
  179.     return val;
  180. }
  181.  
  182. /** Enable interrupts.
  183.  *
  184.  * Enable interrupts and return previous
  185.  * value of EFLAGS.
  186.  *
  187.  * @return Old interrupt priority level.
  188.  */
  189. static inline ipl_t interrupts_enable(void)
  190. {
  191.     ipl_t v;
  192.     asm volatile (
  193.         "pushf\n\t"
  194.         "popl %0\n\t"
  195.         "sti\n"
  196.         : "=r" (v)
  197.     );
  198.     return v;
  199. }
  200.  
  201. /** Disable interrupts.
  202.  *
  203.  * Disable interrupts and return previous
  204.  * value of EFLAGS.
  205.  *
  206.  * @return Old interrupt priority level.
  207.  */
  208. static inline ipl_t interrupts_disable(void)
  209. {
  210.     ipl_t v;
  211.     asm volatile (
  212.         "pushf\n\t"
  213.         "popl %0\n\t"
  214.         "cli\n"
  215.         : "=r" (v)
  216.     );
  217.     return v;
  218. }
  219.  
  220. /** Restore interrupt priority level.
  221.  *
  222.  * Restore EFLAGS.
  223.  *
  224.  * @param ipl Saved interrupt priority level.
  225.  */
  226. static inline void interrupts_restore(ipl_t ipl)
  227. {
  228.     asm volatile (
  229.         "pushl %0\n\t"
  230.         "popf\n"
  231.         : : "r" (ipl)
  232.     );
  233. }
  234.  
  235. /** Return interrupt priority level.
  236.  *
  237.  * @return EFLAFS.
  238.  */
  239. static inline ipl_t interrupts_read(void)
  240. {
  241.     ipl_t v;
  242.     asm volatile (
  243.         "pushf\n\t"
  244.         "popl %0\n"
  245.         : "=r" (v)
  246.     );
  247.     return v;
  248. }
  249.  
  250. /** Return base address of current stack
  251.  *
  252.  * Return the base address of the current stack.
  253.  * The stack is assumed to be STACK_SIZE bytes long.
  254.  * The stack must start on page boundary.
  255.  */
  256. static inline uintptr_t get_stack_base(void)
  257. {
  258.     uintptr_t v;
  259.    
  260.     asm volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
  261.    
  262.     return v;
  263. }
  264.  
  265. /** Return current IP address */
  266. static inline uintptr_t * get_ip()
  267. {
  268.     uintptr_t *ip;
  269.  
  270.     asm volatile (
  271.         "mov %%eip, %0"
  272.         : "=r" (ip)
  273.         );
  274.     return ip;
  275. }
  276.  
  277. /** Invalidate TLB Entry.
  278.  *
  279.  * @param addr Address on a page whose TLB entry is to be invalidated.
  280.  */
  281. static inline void invlpg(uintptr_t addr)
  282. {
  283.     asm volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr));
  284. }
  285.  
  286. /** Load GDTR register from memory.
  287.  *
  288.  * @param gdtr_reg Address of memory from where to load GDTR.
  289.  */
  290. static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
  291. {
  292.     asm volatile ("lgdtl %0\n" : : "m" (*gdtr_reg));
  293. }
  294.  
  295. /** Store GDTR register to memory.
  296.  *
  297.  * @param gdtr_reg Address of memory to where to load GDTR.
  298.  */
  299. static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
  300. {
  301.     asm volatile ("sgdtl %0\n" : : "m" (*gdtr_reg));
  302. }
  303.  
  304. /** Load IDTR register from memory.
  305.  *
  306.  * @param idtr_reg Address of memory from where to load IDTR.
  307.  */
  308. static inline void idtr_load(ptr_16_32_t *idtr_reg)
  309. {
  310.     asm volatile ("lidtl %0\n" : : "m" (*idtr_reg));
  311. }
  312.  
  313. /** Load TR from descriptor table.
  314.  *
  315.  * @param sel Selector specifying descriptor of TSS segment.
  316.  */
  317. static inline void tr_load(uint16_t sel)
  318. {
  319.     asm volatile ("ltr %0" : : "r" (sel));
  320. }
  321.  
  322. #endif
  323.  
  324. /** @}
  325.  */
  326.